Approximate Multipliers Using Bio-Inspired Algorithm
As most of the real-world problems are imprecise, dedicating a lot of hardware for precise computations is futile for low-power applications and few applications where the precision is not of paramount importance. For such applications an imprecise computational block is sufficient if it has other p...
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| Vydáno v: | Journal of electrical engineering & technology Ročník 16; číslo 1; s. 559 - 568 |
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| Médium: | Journal Article |
| Jazyk: | angličtina |
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Springer Singapore
01.01.2021
대한전기학회 |
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| ISSN: | 1975-0102, 2093-7423 |
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| Abstract | As most of the real-world problems are imprecise, dedicating a lot of hardware for precise computations is futile for low-power applications and few applications where the precision is not of paramount importance. For such applications an imprecise computational block is sufficient if it has other performance benefits like low power and low area. We propose Constrained Cartesian Genetic Programming (CCGP), a variant of CGP to evolve lower order imprecise multipliers and further the higher order multipliers are constructed from them. Gate-level architectures for 2 × 2, 3 × 2, 3 × 3 and 4 × 4 imprecise multipliers are evolved. Also, we propose few partitioning methodologies for the construction of higher order multipliers using the evolved imprecise lower order multipliers. The constructed evolved-partitioned multiplier (EPM) of orders 8 × 8 and 16 × 16 has significant performance benefits over the existing multiplier architectures in terms of cell area and power. The circuits are synthesized using Cadence SoC Encounter
®
using TSMC
®
180 nm standard cell library. The 16-bit EPMs show a maximum power reduction of 33% compared to other truncated multipliers and an area improvement of 2%. |
|---|---|
| AbstractList | As most of the real-world problems are imprecise, dedicating a lot of hardware for precise computations is futile for lowpower applications and few applications where the precision is not of paramount importance. For such applications an imprecise computational block is suffi cient if it has other performance benefi ts like low power and low area. We propose Constrained Cartesian Genetic Programming (CCGP), a variant of CGP to evolve lower order imprecise multipliers and further the higher order multipliers are constructed from them. Gate-level architectures for 2 × 2, 3 × 2, 3 × 3 and 4 × 4 imprecise multipliers are evolved. Also, we propose few partitioning methodologies for the construction of higher order multipliers using the evolved imprecise lower order multipliers. The constructed evolved-partitioned multiplier (EPM) of orders 8 × 8 and 16 × 16 has signifi cant performance benefi ts over the existing multiplier architectures in terms of cell area and power.
The circuits are synthesized using Cadence SoC Encounter ® using TSMC ® 180 nm standard cell library. The 16-bit EPMs show a maximum power reduction of 33% compared to other truncated multipliers and an area improvement of 2%. KCI Citation Count: 0 As most of the real-world problems are imprecise, dedicating a lot of hardware for precise computations is futile for low-power applications and few applications where the precision is not of paramount importance. For such applications an imprecise computational block is sufficient if it has other performance benefits like low power and low area. We propose Constrained Cartesian Genetic Programming (CCGP), a variant of CGP to evolve lower order imprecise multipliers and further the higher order multipliers are constructed from them. Gate-level architectures for 2 × 2, 3 × 2, 3 × 3 and 4 × 4 imprecise multipliers are evolved. Also, we propose few partitioning methodologies for the construction of higher order multipliers using the evolved imprecise lower order multipliers. The constructed evolved-partitioned multiplier (EPM) of orders 8 × 8 and 16 × 16 has significant performance benefits over the existing multiplier architectures in terms of cell area and power. The circuits are synthesized using Cadence SoC Encounter ® using TSMC ® 180 nm standard cell library. The 16-bit EPMs show a maximum power reduction of 33% compared to other truncated multipliers and an area improvement of 2%. |
| Author | Kumarasamy, Kunaraj Senthilkumar, K. K. Dhandapani, Vaithiyanathan |
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| Cites_doi | 10.1109/ICCD.2017.22 10.1109/ICET.2010.5638462 10.1109/EH.2000.869353 10.1109/ISCAS.2019.8702199 10.1109/CJECE.2013.6704691 10.1109/ETS.2013.6569370 10.7873/DATE.2013.280 10.1109/ICES.2013.6613278 10.1109/ACSSC.2000.911206 10.1109/EH.2004.1310814 10.1166/jolpe.2011.1157 10.1109/TVLSI.2008.2004544 10.1109/EH.1999.785435 10.1145/2228360.2228504 10.1109/ISCAS.2008.4542165 10.1049/iet-cds.2009.0329 10.1109/ACSSC.2005.1599946 |
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| Keywords | Imprecise computation Low power arithmetic Cartesian Genetic Programming Recursive multiplier Evolutionary computation |
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| References | Oltean M, Grosan C (2004) Evolving digital circuits using multi expression programming. In: Proceedings NASA/DoD conference on evolvable hardware, pp 87–94, 24–26 MillerJFJobDVassilevVKPrinciples in the evolutionary design of digital circuits - part lGenet Program Evolvable Mach2000118351035.68640 Irfan M, Habib Q, Hassan GM, Yahya KM, Hayat S (2010) Combinational digital circuit synthesis using Cartesian Genetic Programming from a NAND gate template. In: International conference onemerging technologies (ICET), pp 343–347 Vassilev VK, Miller JE (2000) Towards the automatic design of more efficient digital circuits. In: Evolvable hardware, proceedings. The second NASA/DoD workshop, pp 151–160 Wang S, Wu YW (2003) Minimization of switching activities of partial products for designing low-power multipliers. In: IEEE transactions on very large scale integration (VLSI) systems, vol 11, issue 3, pp 418–433 Chinnery D, Keutzer K (2003) Low power multiplication algorithm for switching activity reduction through operand decomposition. In: Proceedings 21st international conference on computer design, pp 21–26 Shen NY, Chen (2002) Low-power multipliers by minimizing switching activities of partial products. In: IEEE international symposium oncircuits and systems, ISCAS 2002, vol 4, pp 93–96 Vassilev VK, Job D, Miller JF (2000) Towards the automatic design of more efficient digital circuits. In: The second NASA/DoD workshop on evolvable hardware, pp 151–160 Mudassir R, Anis M, Jaffari J (2008) Switching activity reduction in low power Booth multiplier. In: ISCAS 2008, IEEE international symposium on circuits and systems, pp 3306–3309, 18–21 KulkarniPGuptaPMilosDTrading accuracy for power in a multiplier architectureJ Low Power Electron2011749050110.1166/jolpe.2011.1157 Sekanina L, Vasicek Z (2013) Approximate circuit design by means of evolvable hardware. In: IEEE international conference on evolvable systems (SSCI-ICES), IEEE CS, 2013, pp 21–28 Biswas K, Mokrian P, Huapeng W, Ahmadi M (2005) Truncation schemes for recursive multipliers. In: Conference record of the thirty-ninth asilomar conference on signals, systems and computers, pp 1177–1180 Azarmehr M, Ahmadi M, Jullien GA, Muscedere R (2010) High-speed and low-power reconfigurable architectures of 2-digit two-dimensional logarithmic number system-based recursive multipliers. In: Circuits, devices & systems, IET, vol 4, issue 5, pp 374–381 Yang T, Ukezono T, Sato V (2017) Low-power and high-speed approximate multiplier design with a tree compressor. In: IEEE international conference on computer design (ICCD), Boston, MA, pp 89–96 Mohapatra D (2011) Approximate computing: enabling voltage over-scaling in multimedia applications. Ph.D Thesis, Purdue University Venkataramani S, Roy K, Raghunathan A (2013) Substitute-and-simplify: a unified design paradigm for approximate and quality configurable circuits. In: Design, automation & test in Europe conference & exhibition (DATE), pp 1367–1372, 18–22 Kalganova T, Miller J (1999) Evolving more efficient digital circuits by allowing circuit layout evolution and multi-objective fitness. In: Proceedings of the first NASA/DoD workshop on evolvable hardware, pp 54–63 Danysh AN, Swartzlander EE (1998) A recursive fast multiplier. In: Signals, systems & computers, conference record of the thirty-second asilomar conference, vol 1, pp 197–201 Kim J, Swartzlander EE (2000) Improving the recursive multiplier. In: Conference record of the thirty-fourth asilomar conference on signals, systems and computers, vol 2, pp 1320–1324 Wang S, Wu YW, Chen (2000) Low-power multipliers by minimizing inter-data switching activities. In: Proceedings of the 43rd IEEE midwest symposium on circuits and systems, vol 1, pp 88–89 KunarajKSeshasayananRLeading one detectors and leading one position detectors - an evolutionary design methodologyCan J Electr Comput Eng201336310311010.1109/CJECE.2013.6704691 King EJ, Swartzlander EE (1997) Data-dependent truncation scheme for parallel multipliers. In: 31st asilomar conf. signals, syst. computer, vol 2, pp 1178–1182 Han J, Orshansky M (2013) Approximate computing: an emerging paradigm for energy-efficient design. In: 18th IEEE European test symposium (ETS), pp 1, 6, 27 Kunaraj K, Seshasayanan R (2014) Constrained cartesian genetic programming - a new paradigm for evolving imprecise multipliers. In: International journal on numerical and analytical methods in engineering, vol 2, issue 1, pp 5–8 Yi X, Pei H, Zhang Z, Zhou H, He Y (2019) Design of an energy-efficient approximate compressor for error-resilient multiplications. In: IEEE international symposium on circuits and systems (ISCAS), pp 1–5 Hong CC, Satzoda RK (2010) A low error and high performance multiplexer-based truncated multiplier. In: IEEE transactions on very large scale integration (VLSI) systems, vol 18, issue 12, pp 1767–1771 Mottaghi-Dastjerdi M, Afzali-Kusha A, Pedram M (2009) BZ-FAD: a low-power low-area multiplier based on shift-and-add architecture. In: IEEE transactions on very large scale integration (VLSI) systems, vol 17, issue 2, pp 302–306 Vassilev VK, Miller JE (2000) Scalability problems of digital circuit evolution evolvability and efficient designs. In: Evolvable hardware, proceedings. The second NASA/DoD workshop on evolvable hardware, pp 55–64 Venkataramani S, Sabne A, Kozhikkottu V, Raghunathan A (2012) SALSA: systematic logic synthesis of approximate circuits. In: 49th ACM/EDAC/IEEE design automation conference (DAC), pp 796–801 564_CR3 564_CR4 564_CR5 564_CR6 564_CR7 564_CR28 564_CR8 564_CR9 564_CR29 564_CR1 564_CR2 JF Miller (564_CR18) 2000; 1 564_CR13 564_CR12 564_CR15 564_CR14 564_CR11 564_CR10 K Kunaraj (564_CR26) 2013; 36 564_CR17 P Kulkarni (564_CR27) 2011; 7 564_CR16 564_CR19 564_CR24 564_CR23 564_CR25 564_CR20 564_CR22 564_CR21 |
| References_xml | – reference: Mohapatra D (2011) Approximate computing: enabling voltage over-scaling in multimedia applications. Ph.D Thesis, Purdue University – reference: Venkataramani S, Roy K, Raghunathan A (2013) Substitute-and-simplify: a unified design paradigm for approximate and quality configurable circuits. In: Design, automation & test in Europe conference & exhibition (DATE), pp 1367–1372, 18–22 – reference: Irfan M, Habib Q, Hassan GM, Yahya KM, Hayat S (2010) Combinational digital circuit synthesis using Cartesian Genetic Programming from a NAND gate template. In: International conference onemerging technologies (ICET), pp 343–347 – reference: Chinnery D, Keutzer K (2003) Low power multiplication algorithm for switching activity reduction through operand decomposition. In: Proceedings 21st international conference on computer design, pp 21–26 – reference: Azarmehr M, Ahmadi M, Jullien GA, Muscedere R (2010) High-speed and low-power reconfigurable architectures of 2-digit two-dimensional logarithmic number system-based recursive multipliers. In: Circuits, devices & systems, IET, vol 4, issue 5, pp 374–381 – reference: Kim J, Swartzlander EE (2000) Improving the recursive multiplier. In: Conference record of the thirty-fourth asilomar conference on signals, systems and computers, vol 2, pp 1320–1324 – reference: Wang S, Wu YW, Chen (2000) Low-power multipliers by minimizing inter-data switching activities. In: Proceedings of the 43rd IEEE midwest symposium on circuits and systems, vol 1, pp 88–89 – reference: Hong CC, Satzoda RK (2010) A low error and high performance multiplexer-based truncated multiplier. In: IEEE transactions on very large scale integration (VLSI) systems, vol 18, issue 12, pp 1767–1771 – reference: KulkarniPGuptaPMilosDTrading accuracy for power in a multiplier architectureJ Low Power Electron2011749050110.1166/jolpe.2011.1157 – reference: Biswas K, Mokrian P, Huapeng W, Ahmadi M (2005) Truncation schemes for recursive multipliers. In: Conference record of the thirty-ninth asilomar conference on signals, systems and computers, pp 1177–1180 – reference: Oltean M, Grosan C (2004) Evolving digital circuits using multi expression programming. In: Proceedings NASA/DoD conference on evolvable hardware, pp 87–94, 24–26 – reference: Vassilev VK, Job D, Miller JF (2000) Towards the automatic design of more efficient digital circuits. In: The second NASA/DoD workshop on evolvable hardware, pp 151–160 – reference: Vassilev VK, Miller JE (2000) Towards the automatic design of more efficient digital circuits. In: Evolvable hardware, proceedings. The second NASA/DoD workshop, pp 151–160 – reference: Han J, Orshansky M (2013) Approximate computing: an emerging paradigm for energy-efficient design. In: 18th IEEE European test symposium (ETS), pp 1, 6, 27 – reference: Shen NY, Chen (2002) Low-power multipliers by minimizing switching activities of partial products. In: IEEE international symposium oncircuits and systems, ISCAS 2002, vol 4, pp 93–96 – reference: MillerJFJobDVassilevVKPrinciples in the evolutionary design of digital circuits - part lGenet Program Evolvable Mach2000118351035.68640 – reference: Yi X, Pei H, Zhang Z, Zhou H, He Y (2019) Design of an energy-efficient approximate compressor for error-resilient multiplications. In: IEEE international symposium on circuits and systems (ISCAS), pp 1–5 – reference: Sekanina L, Vasicek Z (2013) Approximate circuit design by means of evolvable hardware. In: IEEE international conference on evolvable systems (SSCI-ICES), IEEE CS, 2013, pp 21–28 – reference: KunarajKSeshasayananRLeading one detectors and leading one position detectors - an evolutionary design methodologyCan J Electr Comput Eng201336310311010.1109/CJECE.2013.6704691 – reference: Kunaraj K, Seshasayanan R (2014) Constrained cartesian genetic programming - a new paradigm for evolving imprecise multipliers. In: International journal on numerical and analytical methods in engineering, vol 2, issue 1, pp 5–8 – reference: Mudassir R, Anis M, Jaffari J (2008) Switching activity reduction in low power Booth multiplier. In: ISCAS 2008, IEEE international symposium on circuits and systems, pp 3306–3309, 18–21 – reference: Mottaghi-Dastjerdi M, Afzali-Kusha A, Pedram M (2009) BZ-FAD: a low-power low-area multiplier based on shift-and-add architecture. In: IEEE transactions on very large scale integration (VLSI) systems, vol 17, issue 2, pp 302–306 – reference: Wang S, Wu YW (2003) Minimization of switching activities of partial products for designing low-power multipliers. In: IEEE transactions on very large scale integration (VLSI) systems, vol 11, issue 3, pp 418–433 – reference: King EJ, Swartzlander EE (1997) Data-dependent truncation scheme for parallel multipliers. In: 31st asilomar conf. signals, syst. computer, vol 2, pp 1178–1182 – reference: Venkataramani S, Sabne A, Kozhikkottu V, Raghunathan A (2012) SALSA: systematic logic synthesis of approximate circuits. In: 49th ACM/EDAC/IEEE design automation conference (DAC), pp 796–801 – reference: Yang T, Ukezono T, Sato V (2017) Low-power and high-speed approximate multiplier design with a tree compressor. In: IEEE international conference on computer design (ICCD), Boston, MA, pp 89–96 – reference: Vassilev VK, Miller JE (2000) Scalability problems of digital circuit evolution evolvability and efficient designs. In: Evolvable hardware, proceedings. The second NASA/DoD workshop on evolvable hardware, pp 55–64 – reference: Danysh AN, Swartzlander EE (1998) A recursive fast multiplier. In: Signals, systems & computers, conference record of the thirty-second asilomar conference, vol 1, pp 197–201 – reference: Kalganova T, Miller J (1999) Evolving more efficient digital circuits by allowing circuit layout evolution and multi-objective fitness. In: Proceedings of the first NASA/DoD workshop on evolvable hardware, pp 54–63 – ident: 564_CR28 doi: 10.1109/ICCD.2017.22 – ident: 564_CR14 doi: 10.1109/ICET.2010.5638462 – ident: 564_CR19 doi: 10.1109/EH.2000.869353 – ident: 564_CR20 – ident: 564_CR29 doi: 10.1109/ISCAS.2019.8702199 – volume: 36 start-page: 103 issue: 3 year: 2013 ident: 564_CR26 publication-title: Can J Electr Comput Eng doi: 10.1109/CJECE.2013.6704691 – ident: 564_CR24 – ident: 564_CR8 – ident: 564_CR21 doi: 10.1109/ETS.2013.6569370 – ident: 564_CR2 – ident: 564_CR6 – ident: 564_CR16 – ident: 564_CR23 doi: 10.7873/DATE.2013.280 – ident: 564_CR25 doi: 10.1109/ICES.2013.6613278 – ident: 564_CR4 doi: 10.1109/ACSSC.2000.911206 – ident: 564_CR9 doi: 10.1109/EH.2004.1310814 – ident: 564_CR7 – volume: 7 start-page: 490 year: 2011 ident: 564_CR27 publication-title: J Low Power Electron doi: 10.1166/jolpe.2011.1157 – ident: 564_CR12 doi: 10.1109/TVLSI.2008.2004544 – ident: 564_CR15 doi: 10.1109/EH.1999.785435 – ident: 564_CR22 doi: 10.1145/2228360.2228504 – ident: 564_CR11 doi: 10.1109/ISCAS.2008.4542165 – ident: 564_CR13 doi: 10.1049/iet-cds.2009.0329 – ident: 564_CR1 – ident: 564_CR3 – volume: 1 start-page: 8 issue: 1 year: 2000 ident: 564_CR18 publication-title: Genet Program Evolvable Mach – ident: 564_CR5 – ident: 564_CR10 doi: 10.1109/ACSSC.2005.1599946 – ident: 564_CR17 |
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| Title | Approximate Multipliers Using Bio-Inspired Algorithm |
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