Automatic residue-to-binary converter circuit generation and simplification using hybrid cartesian genetic programming and simulated annealing

Residue Number Systems (RNS) provide notable advantages in digital signal processing and error detection due to their inherent parallelism and fault tolerance. However, designing efficient reverse converters, particularly those based on the Chinese Remainder Theorem, remains a complex and labour-int...

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Bibliographic Details
Published in:	Expert systems with applications Vol. 296; p. 129083
Main Authors:	Dadashzadeh, Amir, Hosseizadeh, Mehdi, Molahosseini, Amir Sabbagh, Sahafi, Amir
Format:	Journal Article
Language:	English
Published:	Elsevier Ltd 15.01.2026
Subjects:	Cartesian Genetic Programming (CGP) Eevolutionary Circuit Design Residue Number Systems (RNS) Reverse Converter Simplification of RNS Converters Residue Number Systems (RNS) Simplification of RNS Converters Reverse Converter Cartesian Genetic Programming (CGP) Eevolutionary Circuit Design
ISSN:	0957-4174
Online Access:	Get full text
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Summary:	Residue Number Systems (RNS) provide notable advantages in digital signal processing and error detection due to their inherent parallelism and fault tolerance. However, designing efficient reverse converters, particularly those based on the Chinese Remainder Theorem, remains a complex and labour-intensive. This paper presents an innovative automated methodology for developing simplified residue-to-binary converters by integrating Cartesian Genetic Programming (CGP) with Simulated Annealing (SA). The proposed approach employs a two-phase optimization framework. In the first phase, a hybrid CGP-SA algorithm generates module-level architectures by evolving computational structures using arithmetic and bitwise operations. Then, SA is then applied to optimize operator parameters, ensuring functional accuracy and enhanced efficiency. In the second phase, the high-level architecture is refined into an optimized gate-level design using adaptive evolutionary strategies to minimize latency, area, and power consumption. Simulation results demonstrate that the proposed framework consistently outperforms conventional handcrafted methods, offering improved computational efficiency, reduced hardware complexity, and greater design flexibility. This advancement provides a promising solution for practical, high-performance RNS reverse converter implementations.
ISSN:	0957-4174
DOI:	10.1016/j.eswa.2025.129083