Automatic residue-to-binary converter circuit generation and simplification using hybrid cartesian genetic programming and simulated annealing
Residue Number Systems (RNS) provide notable advantages in digital signal processing and error detection due to their inherent parallelism and fault tolerance. However, designing efficient reverse converters, particularly those based on the Chinese Remainder Theorem, remains a complex and labour-int...
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| Veröffentlicht in: | Expert systems with applications Jg. 296; S. 129083 |
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| Abstract | Residue Number Systems (RNS) provide notable advantages in digital signal processing and error detection due to their inherent parallelism and fault tolerance. However, designing efficient reverse converters, particularly those based on the Chinese Remainder Theorem, remains a complex and labour-intensive. This paper presents an innovative automated methodology for developing simplified residue-to-binary converters by integrating Cartesian Genetic Programming (CGP) with Simulated Annealing (SA). The proposed approach employs a two-phase optimization framework. In the first phase, a hybrid CGP-SA algorithm generates module-level architectures by evolving computational structures using arithmetic and bitwise operations. Then, SA is then applied to optimize operator parameters, ensuring functional accuracy and enhanced efficiency. In the second phase, the high-level architecture is refined into an optimized gate-level design using adaptive evolutionary strategies to minimize latency, area, and power consumption. Simulation results demonstrate that the proposed framework consistently outperforms conventional handcrafted methods, offering improved computational efficiency, reduced hardware complexity, and greater design flexibility. This advancement provides a promising solution for practical, high-performance RNS reverse converter implementations. |
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| AbstractList | Residue Number Systems (RNS) provide notable advantages in digital signal processing and error detection due to their inherent parallelism and fault tolerance. However, designing efficient reverse converters, particularly those based on the Chinese Remainder Theorem, remains a complex and labour-intensive. This paper presents an innovative automated methodology for developing simplified residue-to-binary converters by integrating Cartesian Genetic Programming (CGP) with Simulated Annealing (SA). The proposed approach employs a two-phase optimization framework. In the first phase, a hybrid CGP-SA algorithm generates module-level architectures by evolving computational structures using arithmetic and bitwise operations. Then, SA is then applied to optimize operator parameters, ensuring functional accuracy and enhanced efficiency. In the second phase, the high-level architecture is refined into an optimized gate-level design using adaptive evolutionary strategies to minimize latency, area, and power consumption. Simulation results demonstrate that the proposed framework consistently outperforms conventional handcrafted methods, offering improved computational efficiency, reduced hardware complexity, and greater design flexibility. This advancement provides a promising solution for practical, high-performance RNS reverse converter implementations. |
| ArticleNumber | 129083 |
| Author | Molahosseini, Amir Sabbagh Sahafi, Amir Hosseizadeh, Mehdi Dadashzadeh, Amir |
| Author_xml | – sequence: 1 givenname: Amir surname: Dadashzadeh fullname: Dadashzadeh, Amir email: amir.dadashzadeh@iau.ac.ir organization: Department of Computer Engineering, SR.C., Islamic Azad University, Tehran 1477893855, Iran – sequence: 2 givenname: Mehdi surname: Hosseizadeh fullname: Hosseizadeh, Mehdi email: mehdihosseinzadeh@duytan.edu.vn organization: Institute of Research and Development, Duy Tan University, Da Nang, Vietnam – sequence: 3 givenname: Amir Sabbagh surname: Molahosseini fullname: Molahosseini, Amir Sabbagh email: a.sabbaghmolahosseini@qub.ac.uk organization: School of Electronics, Electrical Engineering and Computer Science, Queen’s University Belfast, Belfast BT9 5AF, UK – sequence: 4 givenname: Amir surname: Sahafi fullname: Sahafi, Amir email: sahafi@iau.ac.ir organization: Department of Computer Engineering, ST.C., Islamic Azad University, Tehran, Iran |
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| Cites_doi | 10.1080/09747338.2015.1115378 10.1109/TCAD.2023.3250603 10.1080/03772063.2024.2352147 10.1016/j.camwa.2007.04.028 10.29292/jics.v17i1.546 10.1016/j.compeleceng.2023.108654 10.1007/s12065-020-00421-9 10.52547/mjee.15.3.93 10.1080/24751839.2023.2272484 10.1016/j.sysarc.2008.03.006 10.3390/e24020242 10.1016/S1383-7621(03)00062-6 10.1109/TEVC.2014.2336175 10.1007/s10623-022-01175-4 10.1007/s10710-019-09360-6 10.1007/978-3-031-42202-7 10.1186/s13634-023-01037-8 10.1109/TCSI.2009.2026681 10.1049/2024/6623637 10.1002/cta.3594 10.1049/iet-cdt.2012.0148 10.46586/tches.v2024.i1.563-591 10.1007/s10710-023-09476-w 10.1016/j.compeleceng.2023.108854 10.3390/app142311153 10.1007/s10710-020-09376-3 10.1007/s11265-017-1238-6 10.1007/s00034-021-01743-4 |
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| Keywords | Residue Number Systems (RNS) Simplification of RNS Converters Reverse Converter Cartesian Genetic Programming (CGP) Eevolutionary Circuit Design |
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