HALTRAV: Design of a High-Performance and Area-Efficient Latch With Triple-Node-Upset Recovery and Algorithm-Based Verifications

With the rapid advancement of semiconductor technologies, latches become increasingly sensitive to soft errors, especially triple node upsets (TNUs), in harsh radiation environments. In this article, we first propose a high-performance and area-efficient latch, namely, HALTRAV, featuring complete TN...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems Jg. 44; H. 6; S. 2367 - 2377
Hauptverfasser:	Guo, Xing, Zhang, Jiajia, Meng, Xu, Li, Zhenmin, Wen, Xiaoqing, Girard, Patrick, Liang, Bin, Yan, Aibin
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.06.2025 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Algorithm-based verification Algorithms Computer science Delay Delays Design automation Electronic design automation Engineering Sciences Integrated circuit reliability Inverters latch design Latches Micro and nanotechnologies Microelectronics Nodes Radiation hardening (electronics) Recovery Reliability engineering Simulation Soft errors source-drain cross-coupled inverters (SCIs) Transistors triple node upset (TNU) Verification Algorithm-based verification Triple node upset Latch design Source-drain cross-coupled inverters
ISSN:	0278-0070, 1937-4151
Online-Zugang:	Volltext
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