Simulate and Eliminate: A Top-to-Bottom Design Methodology for Automatic Generation of Application Specific Architectures

There is an increasing trend toward application specific processing, particularly in embedded computing devices that have stringent performance requirements. Achieving the desired area and throughput constraints requires careful tuning of the underlying architecture and high-level design tools are g...

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Vydáno v:IEEE transactions on computer-aided design of integrated circuits and systems Ročník 30; číslo 8; s. 1173 - 1183
Hlavní autoři: Irturk, A., Matai, J., Oberg, J., Su, J., Kastner, R.
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York IEEE 01.08.2011
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
Algorithm design and analysis
Application specific processor
C (programming language)
Computer architecture
Computer simulation
Design engineering
Digital signal processing
high-level synthesis
MATLAB
Methodology
Optimization
Parametrization
Registers
Signal processing algorithms
Studies
Tuning
ISSN:0278-0070, 1937-4151
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Shrnutí:There is an increasing trend toward application specific processing, particularly in embedded computing devices that have stringent performance requirements. Achieving the desired area and throughput constraints requires careful tuning of the underlying architecture and high-level design tools are gaining increasing acceptance to achieve this goal while decreasing the design time. Most existing tools employ a bottom-to-top methodology, which piece together functional units, interconnect, and control logic based on the given application; this tends to scale poorly. We developed a tool, simulate and eliminate (S&E), that is fundamentally different from the existing high-level design tools as it employs a top-to-bottom methodology. S&E provides automatic generation of a variety of general purpose processing cores with different parameterization options. Then, the provided application(s) are simulated on this general-purpose architecture and the unneeded functionality is eliminated resulting in application specific architecture. S&E generates completely synthesizable hardware description language for an input C and/or MATLAB code. S&E provides different design methods and parameterization options to enable the user to study area and performance tradeoffs over a large number of different architectures and find the optimum architecture for the desired objective.
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ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2011.2120990