Irturk, A., Matai, J., Oberg, J., Su, J., & Kastner, R. (2011). Simulate and Eliminate: A Top-to-Bottom Design Methodology for Automatic Generation of Application Specific Architectures. IEEE transactions on computer-aided design of integrated circuits and systems, 30(8), 1173-1183. https://doi.org/10.1109/TCAD.2011.2120990
Citace podle Chicago (17th ed.)Irturk, A., J. Matai, J. Oberg, J. Su, a R. Kastner. "Simulate and Eliminate: A Top-to-Bottom Design Methodology for Automatic Generation of Application Specific Architectures." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems 30, no. 8 (2011): 1173-1183. https://doi.org/10.1109/TCAD.2011.2120990.
Citace podle MLA (9th ed.)Irturk, A., et al. "Simulate and Eliminate: A Top-to-Bottom Design Methodology for Automatic Generation of Application Specific Architectures." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 30, no. 8, 2011, pp. 1173-1183, https://doi.org/10.1109/TCAD.2011.2120990.