Direct Neural-Network Hardware-Implementation Algorithm

An algorithm for compact neural-network hardware implementation is presented, which exploits the special properties of the Boolean functions describing the operation of artificial neurons with step activation function. The algorithm contains three steps: artificial-neural-network (ANN) mathematical...

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Veröffentlicht in:	IEEE transactions on industrial electronics (1982) Jg. 57; H. 5; S. 1845 - 1848
Hauptverfasser:	Dinu, Andrei, Cirstea, Marcian N, Cirstea, Silvia E
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.05.2010 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Activation Algorithms Artificial neural networks Boolean functions Bridge circuits Digitization Field-programmable gate array (FPGA) Hardware Hardware design languages hardware implementation Integrated circuit packaging Learning theory Logic gates Mathematical analysis Mathematical model Mathematical models Neural networks Neurons Software design Very high speed integrated circuits
ISSN:	0278-0046, 1557-9948
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Abstract	An algorithm for compact neural-network hardware implementation is presented, which exploits the special properties of the Boolean functions describing the operation of artificial neurons with step activation function. The algorithm contains three steps: artificial-neural-network (ANN) mathematical model digitization, conversion of the digitized model into a logic-gate structure, and hardware optimization by elimination of redundant logic gates. A set of C++ programs automates algorithm implementation, generating an optimized very high speed integrated circuit hardware description language code. This strategy bridges the gap between ANN design software and hardware design packages (Xilinx). Although the method is directly applicable only to neurons with step activation functions, it can be extended to sigmoidal functions.
AbstractList	An algorithm for compact neural-network hardware implementation is presented, which exploits the special properties of the Boolean functions describing the operation of artificial neurons with step activation function. The algorithm contains three steps: artificial-neural-network (ANN) mathematical model digitization, conversion of the digitized model into a logic-gate structure, and hardware optimization by elimination of redundant logic gates. A set of C++ programs automates algorithm implementation, generating an optimized very high speed integrated circuit hardware description language code. This strategy bridges the gap between ANN design software and hardware design packages (Xilinx). Although the method is directly applicable only to neurons with step activation functions, it can be extended to sigmoidal functions.
Author	Cirstea, Marcian N Dinu, Andrei Cirstea, Silvia E
Author_xml	– sequence: 1 givenname: Andrei surname: Dinu fullname: Dinu, Andrei email: andrei.dinu@goodrich.com organization: Goodrich Corp., Birmingham, UK – sequence: 2 givenname: Marcian N surname: Cirstea fullname: Cirstea, Marcian N email: marcian@ieee.org organization: Anglia Ruskin Univ., Cambridge, UK – sequence: 3 givenname: Silvia E surname: Cirstea fullname: Cirstea, Silvia E email: silvia.cirstea@anglia.ac.uk organization: Anglia Ruskin Univ., Cambridge, UK
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Cites_doi	10.1109/TIE.2007.911946 10.1109/PCC.2002.998107 10.1109/TIE.2007.898281 10.1109/TIE.2006.888683 10.1109/TIE.2008.2003319 10.1109/TIE.2008.917161 10.1109/ISIE.2007.4374572 10.1109/TIE.2007.898279
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SubjectTerms	Activation Algorithms Artificial neural networks Boolean functions Bridge circuits Digitization Field-programmable gate array (FPGA) Hardware Hardware design languages hardware implementation Integrated circuit packaging Learning theory Logic gates Mathematical analysis Mathematical model Mathematical models Neural networks Neurons Software design Very high speed integrated circuits
Title	Direct Neural-Network Hardware-Implementation Algorithm
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