Laser Fine-Tuneable Deep-Submicrometer CMOS 14-bit DAC - Marche, D.; Savaria, Y.; Gagnon, Y. (IEEE transactions on circuits and systems. I, Regular papers, 2008)
The ever-shrinking CMOS technology favors digital circuitry but imposes a challenge to the analog designer faced with limitations such as process gradients and random device variations. However, the trend to greater integration and systems-on- chips (SoCs), requires that digital and analog blocks be merged into single chips. High resolution digital-analog converters (DACs) are especially sensitive to the final matching of components and their nominal accuracy is typically enhanced with additional calibration circuitry or laser trimming. Additional calibration circuits increase cost significantly and mainstream laser trimming technique is applied on thin film resistive layers that are not available with most standard fabrication processes used for SoC. In this paper, we present a high-resolution DAC taking advantage of a new laser trimming technique which is compatible with standard CMOS processes, and that can be integrated in SoCs. While initial mismatch prevents reaching the targeted 14-bit resolution, the included tuning elements offer the necessary calibration to exceed the matching requirements and obtain the desired DAC linearity. The architecture of the DAC itself is a classic current-mode segmented resistor ladder: an inverted R2R ladder generating the binary weighted least significant bit currents is combined with unary current sources for the thermometer encoded most significant bits. The entire structure is precisely calibrated to obtain the final desired linearity. The effectiveness of the trimming technology and its application to high-accuracy DACs is demonstrated.