Laser Fine-Tuneable Deep-Submicrometer CMOS 14-bit DAC

The ever-shrinking CMOS technology favors digital circuitry but imposes a challenge to the analog designer faced with limitations such as process gradients and random device variations. However, the trend to greater integration and systems-on- chips (SoCs), requires that digital and analog blocks be...

Celý popis

Uloženo v:
Podrobná bibliografie
Vydáno v:IEEE transactions on circuits and systems. I, Regular papers Ročník 55; číslo 8; s. 2157 - 2165
Hlavní autoři: Marche, D., Savaria, Y., Gagnon, Y.
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York IEEE 01.09.2008
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
Analog integrated circuits
Calibration
CMOS
CMOS analog integrated circuits
CMOS digital integrated circuits
CMOS process
CMOS technology
Costs
data converter
digital-analog conversion (DAC)
laser trimming
Laser tuning
Linearity
Microelectronics
Optical design
R2R ladder
Thin film circuits
ISSN:1549-8328, 1558-0806
On-line přístup:Získat plný text
Tagy: Přidat tag
Žádné tagy, Buďte první, kdo vytvoří štítek k tomuto záznamu!
Popis
Shrnutí:The ever-shrinking CMOS technology favors digital circuitry but imposes a challenge to the analog designer faced with limitations such as process gradients and random device variations. However, the trend to greater integration and systems-on- chips (SoCs), requires that digital and analog blocks be merged into single chips. High resolution digital-analog converters (DACs) are especially sensitive to the final matching of components and their nominal accuracy is typically enhanced with additional calibration circuitry or laser trimming. Additional calibration circuits increase cost significantly and mainstream laser trimming technique is applied on thin film resistive layers that are not available with most standard fabrication processes used for SoC. In this paper, we present a high-resolution DAC taking advantage of a new laser trimming technique which is compatible with standard CMOS processes, and that can be integrated in SoCs. While initial mismatch prevents reaching the targeted 14-bit resolution, the included tuning elements offer the necessary calibration to exceed the matching requirements and obtain the desired DAC linearity. The architecture of the DAC itself is a classic current-mode segmented resistor ladder: an inverted R2R ladder generating the binary weighted least significant bit currents is combined with unary current sources for the thermometer encoded most significant bits. The entire structure is precisely calibrated to obtain the final desired linearity. The effectiveness of the trimming technology and its application to high-accuracy DACs is demonstrated.
Bibliografie:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ObjectType-Article-2
ObjectType-Feature-1
content type line 23
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2008.920152