Visconti, P., Capoccia, S., Venere, E., Velázquez, R., & Fazio, R. d. (2020). 10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform. Electronics (Basel), 9(10), 1665. https://doi.org/10.3390/electronics9101665
Citace podle Chicago (17th ed.)Visconti, Paolo, Stefano Capoccia, Eugenio Venere, Ramiro Velázquez, a Roberto de Fazio. "10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm Up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform." Electronics (Basel) 9, no. 10 (2020): 1665. https://doi.org/10.3390/electronics9101665.
Citace podle MLA (9th ed.)Visconti, Paolo, et al. "10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm Up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform." Electronics (Basel), vol. 9, no. 10, 2020, p. 1665, https://doi.org/10.3390/electronics9101665.