Performance analysis of Vedic mathematics algorithms on re-configurable hardware platform
For the overall performance of systems like microprocessors and digital signal processors (DSPs) platforms, arithmetic units, all must be efficient in terms of speed, power, and area. Multipliers and dividers are inevitable hardware employed in such systems. This paper focuses on Vedic mathematics a...
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| Published in: | Sadhana (Bangalore) Vol. 46; no. 2 |
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| Language: | English |
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01.06.2021
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| Abstract | For the overall performance of systems like microprocessors and digital signal processors (DSPs) platforms, arithmetic units, all must be efficient in terms of speed, power, and area. Multipliers and dividers are inevitable hardware employed in such systems. This paper focuses on Vedic mathematics algorithms for multiplication and division for power-efficient, faster, and area-efficient design. For four- and eight-bit Vedic multiplication algorithms, Urdhva Tiryagbhyam and Nikhilam Sutras are employed in this paper. For eight-bit Vedic division algorithms, Nikhilam and Dhwajank Sutras are used. The Vedic mathematics algorithms are also compared to conventional methods of multiplication (like Array multiplier) and division (using Booth multiplication algorithm). As an application of DSP, the linear convolution operation is implemented using both conventional and Vedic algorithms. It has been observed that the Vedic algorithms operate faster, consume less power, and occupy less area on a targeted hardware platform. The implementations were carried out using the Verilog HDL language and Xilinx’s Vivado EDA tool. To measure various performance parameters, Cadence simvision (using 180-nm GPDK CMOS Technology) and Xilinx’s ISE tool were also used. |
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| AbstractList | For the overall performance of systems like microprocessors and digital signal processors (DSPs) platforms, arithmetic units, all must be efficient in terms of speed, power, and area. Multipliers and dividers are inevitable hardware employed in such systems. This paper focuses on Vedic mathematics algorithms for multiplication and division for power-efficient, faster, and area-efficient design. For four- and eight-bit Vedic multiplication algorithms, Urdhva Tiryagbhyam and Nikhilam Sutras are employed in this paper. For eight-bit Vedic division algorithms, Nikhilam and Dhwajank Sutras are used. The Vedic mathematics algorithms are also compared to conventional methods of multiplication (like Array multiplier) and division (using Booth multiplication algorithm). As an application of DSP, the linear convolution operation is implemented using both conventional and Vedic algorithms. It has been observed that the Vedic algorithms operate faster, consume less power, and occupy less area on a targeted hardware platform. The implementations were carried out using the Verilog HDL language and Xilinx’s Vivado EDA tool. To measure various performance parameters, Cadence simvision (using 180-nm GPDK CMOS Technology) and Xilinx’s ISE tool were also used. |
| ArticleNumber | 83 |
| Author | Savani, Vijay Biji, Rhea |
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| References | Kishor D R and Bhaaskaran V K 2014 Low power divider using vedic mathematics. In: Proceedings of the 2014 International Conference on Advances in Computing, Communications and Informatics (ICACCI), IEEE, pp. 575–580 Sriraman L and Prabakar T N 2012 Design and implementation of two variable multiplier using KCM and vedic mathematics. In: Proceedings of the 2012 1st International Conference on Recent Advances in Information Technology (RAIT), IEEE, pp. 782–787 PunwantwarNRChaturPNConvolution and deconvolution using vedic mathematicsInternational Journal of Advanced Research in Electrical, Electronics, and Instrumentation Engineering2015465216522310.15662/ijareeie.2015.0406042 Neelisha Batham and Shaista AnjumAlgorithm for convolution operation in DFT using vedic multiplicationInternational Journal of Engineering Innovations and Research201655288291 Akhter S, Saini V and Saini J 2017 Analysis of vedic multiplier using various adder topologies. In: Proceedings of the 2017 4th International Conference on Signal Processing and Integrated Networks (SPIN), IEEE, pp. 173–176 KumarAniketComparative analysis of vedic and array multiplierInternational Journal of Electronics and Communication Engineering and Technology2017831727 KumarUgra MohanKumarSandeepSinghMadan PalYadavAshok KumarFast and efficient division technique using vedic mathematics in Verilog codeInternational Journal of Scientific and Engineering Research201781099103 Prasada G S V, Seshikala G, and Niranjana S 2019 Design of high speed 32-bit floating point multiplier using urdhva triyagbhyam sutra of vedic mathematics. International Journal of Recent Technology and Engineering 8(2 special issue 3): 1064–1067 Prasada G S V, Seshikala G, and Sampathila N 2018 Performance analysis of 64×\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times $$\end{document}64 bit multiplier designed using urdhva tiryakbyham and nikhilam navatashcaramam dashatah sutras. In: Proceedings of the 2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), IEEE, pp. 28–31 Toro S, Patil A, Chavan Y V, Patil S C, Bormane D S, and Wadar S 2016 Division operation based on vedic mathematics. In: Proceedings of the 2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT), IEEE, pp. 450–454 Sudeep M C, Bimba M S, and Vucha M 2014 Design and FPGA implementation of high speed vedic multiplier. International Journal of Computer Applications 90(16): 10.5120/15802-4641 Akhter S and Chaturvedi S 2019 Modified binary multiplier circuit based on vedic mathematics. In: Proceedings of the 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN), IEEE, pp. 234–237 Krutika Jayant Sapkal Urmila ShrawankarComplexity analysis of vedic mathematics algorithms for multicore environmentInternational Journal of Rough Sets and Data Analysis20174314710.4018/IJRSDA.2017100103 ThakurKSharmaTArea efficient high speed vedic multiplierInternational Journal of Innovative Technology and Exploring Engineering201989S30230610.35940/ijitee.I1048.0789S19 Rajani M and Sridevi N 2015 Survey on implementation of IEEE754 floating point number division using vedic techniques. International Journal of Engineering Development and Research 3(3) Tadas A and Rotake D 2015 64 bit divider using vedic mathematics. In: Proceedings of the 2015 International Conference on Smart Technologies and Management for Computing, Communication, Controls, Energy and Materials (ICSTM), IEEE, pp. 317–320 Pichhode K, Patil M D, Shah D and Rohit B C 2015 FPGA implementation of efficient vedic multiplier. In: Proceedings of the 2015 International Conference on Information Processing (ICIP), IEEE, pp. 565–570 NR Punwantwar (1605_CR17) 2015; 4 1605_CR1 Ugra Mohan Kumar (1605_CR16) 2017; 8 1605_CR3 1605_CR2 1605_CR15 1605_CR14 1605_CR13 1605_CR12 1605_CR11 Krutika Jayant Sapkal Urmila Shrawankar (1605_CR9) 2017; 4 1605_CR5 Neelisha Batham and Shaista Anjum (1605_CR6) 2016; 5 1605_CR7 Aniket Kumar (1605_CR10) 2017; 8 1605_CR8 K Thakur (1605_CR4) 2019; 8 |
| References_xml | – reference: Sudeep M C, Bimba M S, and Vucha M 2014 Design and FPGA implementation of high speed vedic multiplier. International Journal of Computer Applications 90(16): 10.5120/15802-4641 – reference: KumarUgra MohanKumarSandeepSinghMadan PalYadavAshok KumarFast and efficient division technique using vedic mathematics in Verilog codeInternational Journal of Scientific and Engineering Research201781099103 – reference: Akhter S and Chaturvedi S 2019 Modified binary multiplier circuit based on vedic mathematics. In: Proceedings of the 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN), IEEE, pp. 234–237 – reference: Neelisha Batham and Shaista AnjumAlgorithm for convolution operation in DFT using vedic multiplicationInternational Journal of Engineering Innovations and Research201655288291 – reference: Rajani M and Sridevi N 2015 Survey on implementation of IEEE754 floating point number division using vedic techniques. International Journal of Engineering Development and Research 3(3) – reference: Krutika Jayant Sapkal Urmila ShrawankarComplexity analysis of vedic mathematics algorithms for multicore environmentInternational Journal of Rough Sets and Data Analysis20174314710.4018/IJRSDA.2017100103 – reference: Tadas A and Rotake D 2015 64 bit divider using vedic mathematics. In: Proceedings of the 2015 International Conference on Smart Technologies and Management for Computing, Communication, Controls, Energy and Materials (ICSTM), IEEE, pp. 317–320 – reference: Akhter S, Saini V and Saini J 2017 Analysis of vedic multiplier using various adder topologies. In: Proceedings of the 2017 4th International Conference on Signal Processing and Integrated Networks (SPIN), IEEE, pp. 173–176 – reference: PunwantwarNRChaturPNConvolution and deconvolution using vedic mathematicsInternational Journal of Advanced Research in Electrical, Electronics, and Instrumentation Engineering2015465216522310.15662/ijareeie.2015.0406042 – reference: KumarAniketComparative analysis of vedic and array multiplierInternational Journal of Electronics and Communication Engineering and Technology2017831727 – reference: Prasada G S V, Seshikala G, and Sampathila N 2018 Performance analysis of 64×\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times $$\end{document}64 bit multiplier designed using urdhva tiryakbyham and nikhilam navatashcaramam dashatah sutras. In: Proceedings of the 2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), IEEE, pp. 28–31 – reference: Sriraman L and Prabakar T N 2012 Design and implementation of two variable multiplier using KCM and vedic mathematics. In: Proceedings of the 2012 1st International Conference on Recent Advances in Information Technology (RAIT), IEEE, pp. 782–787 – reference: Toro S, Patil A, Chavan Y V, Patil S C, Bormane D S, and Wadar S 2016 Division operation based on vedic mathematics. In: Proceedings of the 2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT), IEEE, pp. 450–454 – reference: Pichhode K, Patil M D, Shah D and Rohit B C 2015 FPGA implementation of efficient vedic multiplier. In: Proceedings of the 2015 International Conference on Information Processing (ICIP), IEEE, pp. 565–570 – reference: ThakurKSharmaTArea efficient high speed vedic multiplierInternational Journal of Innovative Technology and Exploring Engineering201989S30230610.35940/ijitee.I1048.0789S19 – reference: Kishor D R and Bhaaskaran V K 2014 Low power divider using vedic mathematics. In: Proceedings of the 2014 International Conference on Advances in Computing, Communications and Informatics (ICACCI), IEEE, pp. 575–580 – reference: Prasada G S V, Seshikala G, and Niranjana S 2019 Design of high speed 32-bit floating point multiplier using urdhva triyagbhyam sutra of vedic mathematics. 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| SubjectTerms | Algorithms Arithmetic and logic units CMOS Convolution Digital signal processing Digital signal processors Dividers Dividing (mathematics) Engineering Hardware Mathematical analysis Mathematics Microprocessors Multiplication Multiplication & division Power consumption |
| Title | Performance analysis of Vedic mathematics algorithms on re-configurable hardware platform |
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