ParaLarPD: Parallel FPGA Router Using Primal-Dual Sub-Gradient Method

In the field programmable gate array (FPGA) design flow, one of the most time-consuming steps is the routing of nets. Therefore, there is a need to accelerate it. In a recent work by Hoo et al., the authors have developed a linear programming (LP)-based framework that parallelizes this routing proce...

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Vydané v:	Electronics (Basel) Ročník 8; číslo 12; s. 1439
Hlavní autori:	Agrawal, Rohit, Ahuja, Kapil, Hau Hoo, Chin, Duy Anh Nguyen, Tuan, Kumar, Akash
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	Basel MDPI AG 01.12.2019
Predmet:	Algorithms Critical path Experiments Field programmable gate arrays Iterative algorithms Linear programming Optimization Parallel processing Transistors Wire drawing
ISSN:	2079-9292, 2079-9292
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