APA (7th ed.) Citation

Agrawal, R., Ahuja, K., Hau Hoo, C., Duy Anh Nguyen, T., & Kumar, A. (2019). ParaLarPD: Parallel FPGA Router Using Primal-Dual Sub-Gradient Method. Electronics (Basel), 8(12), 1439. https://doi.org/10.3390/electronics8121439

Chicago Style (17th ed.) Citation

Agrawal, Rohit, Kapil Ahuja, Chin Hau Hoo, Tuan Duy Anh Nguyen, and Akash Kumar. "ParaLarPD: Parallel FPGA Router Using Primal-Dual Sub-Gradient Method." Electronics (Basel) 8, no. 12 (2019): 1439. https://doi.org/10.3390/electronics8121439.

MLA (9th ed.) Citation

Agrawal, Rohit, et al. "ParaLarPD: Parallel FPGA Router Using Primal-Dual Sub-Gradient Method." Electronics (Basel), vol. 8, no. 12, 2019, p. 1439, https://doi.org/10.3390/electronics8121439.