Power optimization of a single-core processor using LSTM based encoder–decoder model for online DVFS - Thethi, Sukhmani Kaur; Kumar, Ravi (Sadhana (Bangalore), 2023)
Due to the interaction and interdependency between various hardware/software units and policies of the processors with application running on it, real-time embedded systems are quite complex in nature. Furthermore, smart adaptability of supply clock and voltage is required in order to optimize power without compromising on the performance, depending upon the type of application running and tasks that the application involved. This is done using Dynamic Voltage and Frequency Scaling (DVFS) technique. A novel DVFS technique is proposed in this paper which models frequency scaling as a recurrent network problem. This approach has successfully been able to capture the intricate dependencies amongst various factors influencing the operation. We employed application independent- Radial Basis Neural Network to generate series of predicted frequencies for current workload of the processor, followed by seq2seq-LSTM based encoder decoder model to decide whether the frequency generated by the ANN model is optimum to conserve power of the embedded device or not. The proposed model predicts the workload and then compares the predicted frequency to the critical value or deadline of the current task pertaining to the application running. The experiments were conducted on a single core processor (RPi Zero) on which a benchmark application named “basicmath” from MiBench suite was run, and promising prediction accuracy rates were obtained without compromising on performance parameter’s degradation.