Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications

In digital signal processing, digital down converters (DDCs) convert digitized, band-limited signals to lower frequency signals at a smaller sampling rate to simplify subsequent filtering stages. Software-defined radio (SDR) is a radio communication system in which components that are traditionally...

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Vydané v:	Circuits, systems, and signal processing Ročník 40; číslo 6; s. 2883 - 2894
Hlavní autori:	Sikka, Prateek, Asati, Abhijit R., Shekhar, Chandra
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York Springer US 01.06.2021 Springer Nature B.V
Predmet:	Applications programs Circuits and Systems Communications systems Converters Design specifications Digital signal processing Electrical Engineering Electronics and Microelectronics Embedded systems Energy conversion efficiency Engineering Field programmable gate arrays Hardware description languages High level synthesis Instrumentation Matlab Power efficiency Power management Radio communications Radio signals Signal processing Signal,Image and Speech Processing Software Software radio High-level synthesis (HLS) MATLAB HDL coder Software-defined radio Hardware description language (HDL) Field programmable gate array (FPGA) Vivado HLS
ISSN:	0278-081X, 1531-5878
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Abstract	In digital signal processing, digital down converters (DDCs) convert digitized, band-limited signals to lower frequency signals at a smaller sampling rate to simplify subsequent filtering stages. Software-defined radio (SDR) is a radio communication system in which components that are traditionally implemented in hardware are implemented in software on an embedded system. DDCs are widely used in modern communication systems, such as SDRs. Herein, we propose a low-power- and area-optimized implementation of a DDC for SDR applications. The DDC was designed using an innovative and novel high-level synthesis (HLS) design method based on application-specific bit widths for data nodes. The results achieved after a field programmable gate array (FPGA) implementation are superior to those obtained from hand-coded register transfer level (RTL) implementations in terms of area and power efficiency, with almost the same speed of operation. Our results were obtained using the MATLAB hardware description language (HDL) coder for HLS and Xilinx Vivado (a software for the synthesis and analysis of HDL designs) for synthesis. The DDC down-converts an input of 200 MHz signal to an output of 2 MHz signal. This implementation was conducted on a real FPGA hardware (Xilinx Kintex-7) and verified against the design specifications using an FPGA in the loop feature of HDL Verifier and MATLAB. In addition, we propose a generic methodology for improving the area, speed, and power for different application designs and HLS tools. The proposed methodology is also applicable to hand-coded RTL designs for any application.
AbstractList	In digital signal processing, digital down converters (DDCs) convert digitized, band-limited signals to lower frequency signals at a smaller sampling rate to simplify subsequent filtering stages. Software-defined radio (SDR) is a radio communication system in which components that are traditionally implemented in hardware are implemented in software on an embedded system. DDCs are widely used in modern communication systems, such as SDRs. Herein, we propose a low-power- and area-optimized implementation of a DDC for SDR applications. The DDC was designed using an innovative and novel high-level synthesis (HLS) design method based on application-specific bit widths for data nodes. The results achieved after a field programmable gate array (FPGA) implementation are superior to those obtained from hand-coded register transfer level (RTL) implementations in terms of area and power efficiency, with almost the same speed of operation. Our results were obtained using the MATLAB hardware description language (HDL) coder for HLS and Xilinx Vivado (a software for the synthesis and analysis of HDL designs) for synthesis. The DDC down-converts an input of 200 MHz signal to an output of 2 MHz signal. This implementation was conducted on a real FPGA hardware (Xilinx Kintex-7) and verified against the design specifications using an FPGA in the loop feature of HDL Verifier and MATLAB. In addition, we propose a generic methodology for improving the area, speed, and power for different application designs and HLS tools. The proposed methodology is also applicable to hand-coded RTL designs for any application. In digital signal processing, digital down converters (DDCs) convert digitized, band-limited signals to lower frequency signals at a smaller sampling rate to simplify subsequent filtering stages. Software-defined radio (SDR) is a radio communication system in which components that are traditionally implemented in hardware are implemented in software on an embedded system. DDCs are widely used in modern communication systems, such as SDRs. Herein, we propose a low-power- and area-optimized implementation of a DDC for SDR applications. The DDC was designed using an innovative and novel high-level synthesis (HLS) design method based on application-specific bit widths for data nodes. The results achieved after a field programmable gate array (FPGA) implementation are superior to those obtained from hand-coded register transfer level (RTL) implementations in terms of area and power efficiency, with almost the same speed of operation. Our results were obtained using the MATLAB hardware description language (HDL) coder for HLS and Xilinx Vivado (a software for the synthesis and analysis of HDL designs) for synthesis. The DDC down-converts an input of 200 MHz signal to an output of 2 MHz signal. This implementation was conducted on a real FPGA hardware (Xilinx Kintex-7) and verified against the design specifications using an FPGA in the loop feature of HDL Verifier and MATLAB. In addition, we propose a generic methodology for improving the area, speed, and power for different application designs and HLS tools. The proposed methodology is also applicable to hand-coded RTL designs for any application.
Author	Shekhar, Chandra Sikka, Prateek Asati, Abhijit R.
Author_xml	– sequence: 1 givenname: Prateek orcidid: 0000-0002-0941-5101 surname: Sikka fullname: Sikka, Prateek email: prateeksikka@gmail.com organization: Electrical and Electronics Engineering Department, Birla Institute of Technology and Science, Vidya Vihar Campus – sequence: 2 givenname: Abhijit R. surname: Asati fullname: Asati, Abhijit R. organization: Electrical and Electronics Engineering Department, Birla Institute of Technology and Science, Vidya Vihar Campus – sequence: 3 givenname: Chandra surname: Shekhar fullname: Shekhar, Chandra organization: Electrical and Electronics Engineering Department, Birla Institute of Technology and Science, Vidya Vihar Campus
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Cites_doi	10.1109/92.238438 10.5937/STR1604040O 10.1007/s00542-019-04579-w 10.1109/TCAD.2011.211059 10.1147/rd.391.0131 10.1109/EDAC.1991.206442 10.1109/54.679205 10.1109/TVLSI.2017.2748603 10.1109/LATINCOM.2017.8240153
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SubjectTerms	Applications programs Circuits and Systems Communications systems Converters Design specifications Digital signal processing Electrical Engineering Electronics and Microelectronics Embedded systems Energy conversion efficiency Engineering Field programmable gate arrays Hardware description languages High level synthesis Instrumentation Matlab Power efficiency Power management Radio communications Radio signals Signal processing Signal,Image and Speech Processing Software Software radio
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Title	Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications
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