Computation of minimal unsatisfiable subformulas for SAT-based digital circuit error diagnosis

The explanation of infeasibilities formed in Minimal Unsatisfiable Subformulas (MUSes) is a core task in the analysis of over-constrained Boolean formulas. A wide range of applications necessitate MUS detection including knowledge-based validation, software design, verification and error diagnosis i...

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Veröffentlicht in:	Journal of ambient intelligence and humanized computing Jg. 13; H. 7; S. 3693 - 3711
Hauptverfasser:	Gaber, Lamya, Hussein, Aziza I., Mahmoud, Hanafy, Mabrook, M. Mourad, Moness, Mohammed
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	Berlin/Heidelberg Springer Berlin Heidelberg 01.07.2022 Springer Nature B.V
Schlagworte:	Algorithms Artificial Intelligence Benchmarks Boolean Canonical forms Central processing units Circuit design Circuits Computation Computational Intelligence CPUs Debugging Design Designers Digital electronics Engineering Graphics processing units Integrated circuits Machine learning Original Research Robotics and Automation Silicon Solvers User Interfaces and Human Computer Interaction Minimal unsatisfiable subsets Boolean satisfiability problem Conjunction normal form GPU Minimal correction subsets SAT solving
ISSN:	1868-5137, 1868-5145
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Abstract	The explanation of infeasibilities formed in Minimal Unsatisfiable Subformulas (MUSes) is a core task in the analysis of over-constrained Boolean formulas. A wide range of applications necessitate MUS detection including knowledge-based validation, software design, verification and error diagnosis in digital VLSI circuits. Consequently, various enhanced algorithms for determining MUS have been utilized for solving Maximum Satisfiability algorithms and Conjunction Normal Form (CNF) redundancies. Three enhancements are proposed in this paper. The first is a CPU-GPU algorithm for computation of Minimal Correction Subsets (MCSes) optimized for NVIDIA General Purpose Graphics Processing Unit paradigm. The proposed algorithm of generating all MCSes from the encoded CNF instance was developed using our parallel SSGPU solver and implemented using CUDA. The second enhancement is an algorithm for MUS computation based on auto-reduction of the enhanced MCSes for faster MUS detection. The third improved algorithm is for computing MUS directly without using MCSes. The two proposed algorithms outperform techniques as they could locate and explain design faults in digital VLSI circuits in earlier stages of IC design flow. The second proposed routine of MUS extraction was performed by avoiding a non-critical step in calling the SAT solver during MUS computation, leading to improving the performance of the MUS extraction algorithm. The third proposed mechanism for direct extraction of MUS was optimized by reducing the required SAT-solver calls using a classification of clauses in the input formula. Comparative analysis of the proposed algorithm against the Compute All Minimal Unsatisfiable Subsets (CAMUS) algorithm determined 1.54 × faster detection of MUS using ISCAS'85, ISCAS'89 and synthetic benchmarks. Also, the third algorithm for direct MUS computation delivers 17.05 × faster than shrinking algorithm used in MUST (minimal unsatisfiable subset) tool using ISCAS'85 and synthetic benchmarks. Moreover, it was observed that the CPU-GPU algorithm for MCSes computation based on the SSGPU solver delivered 1.92 × faster than its conventional counterpart, based on CUD@SAT equivalent on GPU using ISCAS'85, ISCAS'89 and synthetic Benchmarks.
AbstractList	The explanation of infeasibilities formed in Minimal Unsatisfiable Subformulas (MUSes) is a core task in the analysis of over-constrained Boolean formulas. A wide range of applications necessitate MUS detection including knowledge-based validation, software design, verification and error diagnosis in digital VLSI circuits. Consequently, various enhanced algorithms for determining MUS have been utilized for solving Maximum Satisfiability algorithms and Conjunction Normal Form (CNF) redundancies. Three enhancements are proposed in this paper. The first is a CPU-GPU algorithm for computation of Minimal Correction Subsets (MCSes) optimized for NVIDIA General Purpose Graphics Processing Unit paradigm. The proposed algorithm of generating all MCSes from the encoded CNF instance was developed using our parallel SSGPU solver and implemented using CUDA. The second enhancement is an algorithm for MUS computation based on auto-reduction of the enhanced MCSes for faster MUS detection. The third improved algorithm is for computing MUS directly without using MCSes. The two proposed algorithms outperform techniques as they could locate and explain design faults in digital VLSI circuits in earlier stages of IC design flow. The second proposed routine of MUS extraction was performed by avoiding a non-critical step in calling the SAT solver during MUS computation, leading to improving the performance of the MUS extraction algorithm. The third proposed mechanism for direct extraction of MUS was optimized by reducing the required SAT-solver calls using a classification of clauses in the input formula. Comparative analysis of the proposed algorithm against the Compute All Minimal Unsatisfiable Subsets (CAMUS) algorithm determined 1.54 × faster detection of MUS using ISCAS'85, ISCAS'89 and synthetic benchmarks. Also, the third algorithm for direct MUS computation delivers 17.05 × faster than shrinking algorithm used in MUST (minimal unsatisfiable subset) tool using ISCAS'85 and synthetic benchmarks. Moreover, it was observed that the CPU-GPU algorithm for MCSes computation based on the SSGPU solver delivered 1.92 × faster than its conventional counterpart, based on CUD@SAT equivalent on GPU using ISCAS'85, ISCAS'89 and synthetic Benchmarks.
Author	Mabrook, M. Mourad Mahmoud, Hanafy Gaber, Lamya Hussein, Aziza I. Moness, Mohammed
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Keywords	Minimal unsatisfiable subsets Boolean satisfiability problem Conjunction normal form GPU Minimal correction subsets SAT solving
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References_xml	– reference: Shi J, Fey G, Drechsler R, Glowatz A, Hapke F, Schloffel J, PASSAT (2005) Efficient SAT-based test pattern generation for industrial circuits. In: IEEE computer society annual symposium on VLSI: new frontiers in VLSI Design (ISVLSI'05), 212–217. Doi: 10.1109/ISVLSI.2005.55 – reference: NadelARyvchinVStrichmanOAccelerated deletion-based extraction of minimal unsatisfiable coresJ Satisfiability Boolean Modeling Comput201492751329175810.3233/SAT190100 – reference: Ali LG, Hussein AI, Ali HM (2016) Parallelization of unit propagation algorithm for SAT-based ATPG of digital circuits. In: Microelectronics (ICM) 28th international conference 184–188. Doi: 10.1109/ICCES.2017.8275337. – reference: Ren Z, Al-Asaad H (2016) Overview of assertion-based verification and its applications. In: Int'l conf. embedded systems, cyber-physical systems, & applications – reference: AlizadehBBehnamPSadeghi-KohanSA scalable formal debugging approach with auto-correction capability based on static slicing and dynamic ranking for RTL datapath designsIEEE Trans Comput201464615641578335228710.1109/TC.2014.23296871360.68355 – reference: Belov A, Heule M J, Marques-Silva J (2014). MUS extraction using clausal proofs. International Conference on Theory and Applications of Satisfiability Testing, 48-57. https://doi.org/10.1007/978-3-319-09284-3_5 – reference: Le BerreDParrainAThe Sat4j library, release 2.2J Satisfiability Boolean Modeling Comput20107596410.3233/SAT190075 – reference: OsamaMGaberLHusseinAIMahmoudHAn efficient SAT-based test generation algorithm with GPU acceleratorJ Electron Testing20183451152710.1007/s10836-018-5747-4 – reference: SohanghpurwalaAAHassanMWAthanasPHardware accelerated SAT solvers—a surveyJ Parallel Distributed Comput201710617018410.1016/j.jpdc.2016.12.014 – reference: Bendík J, Černá I , Beneš N. (2018). Recursive online enumeration of all minimal unsatisfiable subsets. In: International symposium on automated technology for verification and analysis, pp 143–159. – reference: Bryan D (1985) The ISCAS'85 benchmark circuits and netlist format. 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Snippet	The explanation of infeasibilities formed in Minimal Unsatisfiable Subformulas (MUSes) is a core task in the analysis of over-constrained Boolean formulas. A...
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SubjectTerms	Algorithms Artificial Intelligence Benchmarks Boolean Canonical forms Central processing units Circuit design Circuits Computation Computational Intelligence CPUs Debugging Design Designers Digital electronics Engineering Graphics processing units Integrated circuits Machine learning Original Research Robotics and Automation Silicon Solvers User Interfaces and Human Computer Interaction
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Title	Computation of minimal unsatisfiable subformulas for SAT-based digital circuit error diagnosis
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