Modeling of Doped Fully Depleted Behavior Induced by Total Ionizing Dose in Voltage Reference Circuits From a 65-nm Partially Depleted SOI Technology

In this article, a doped fully depleted silicon on insulator (FDSOI) behavior for the 65-nm partially depleted silicon on insulator (PDSOI) technology is demonstrated to understand the output voltage shift of a voltage reference (VR) undergoing dose deposition in real time. From an in-depth top-bott...

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Vydané v:	IEEE transactions on nuclear science Ročník 72; číslo 4; s. 1276 - 1284
Hlavní autori:	Lomonaco, J., Rostand, N., Martinie, S., Charbonnier, G., Marcandella, C., Bedecarrats, T., Bournel, A.
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York IEEE 01.04.2025 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	CAD Circuits Computer aided design Degradation Depletion Doping Fully depleted silicon on insulator (FDSOI) Integrated circuit modeling Integrated circuits modeling Multiscale analysis partially depleted silicon on insulator (PDSOI) Photonic band gap Predictive models radiation experiments Semiconductor process modeling Silicon Silicon-on-insulator simulation program with integrated circuit emphasis (SPICE) simulation SOI (semiconductors) technology computer aided design (TCAD) Threshold voltage Total ionizing dose total ionizing dose (TID) Transistors Voltage voltage reference (VR)
ISSN:	0018-9499, 1558-1578
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