Modeling of Doped Fully Depleted Behavior Induced by Total Ionizing Dose in Voltage Reference Circuits From a 65-nm Partially Depleted SOI Technology

In this article, a doped fully depleted silicon on insulator (FDSOI) behavior for the 65-nm partially depleted silicon on insulator (PDSOI) technology is demonstrated to understand the output voltage shift of a voltage reference (VR) undergoing dose deposition in real time. From an in-depth top-bott...

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Vydané v:	IEEE transactions on nuclear science Ročník 72; číslo 4; s. 1276 - 1284
Hlavní autori:	Lomonaco, J., Rostand, N., Martinie, S., Charbonnier, G., Marcandella, C., Bedecarrats, T., Bournel, A.
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York IEEE 01.04.2025 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	CAD Circuits Computer aided design Degradation Depletion Doping Fully depleted silicon on insulator (FDSOI) Integrated circuit modeling Integrated circuits modeling Multiscale analysis partially depleted silicon on insulator (PDSOI) Photonic band gap Predictive models radiation experiments Semiconductor process modeling Silicon Silicon-on-insulator simulation program with integrated circuit emphasis (SPICE) simulation SOI (semiconductors) technology computer aided design (TCAD) Threshold voltage Total ionizing dose total ionizing dose (TID) Transistors Voltage voltage reference (VR)
ISSN:	0018-9499, 1558-1578
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Abstract	In this article, a doped fully depleted silicon on insulator (FDSOI) behavior for the 65-nm partially depleted silicon on insulator (PDSOI) technology is demonstrated to understand the output voltage shift of a voltage reference (VR) undergoing dose deposition in real time. From an in-depth top-bottom analysis, including both experiments and technology computer aided design (TCAD)/simulation program with integrated circuit emphasis (SPICE) simulations, we highlighted this unexpected doped FDSOI behavior. This study shows how it worsens the total ionizing dose (TID) effects due to the coupling effect between the front and back interfaces, not usual in this technology. A new threshold voltage model considering channel doping and TID is developed, showing how doping concentration is an important hardening parameter. This model is reused, in a multiscale approach, to reproduce the output voltage shift of a VR based on the PDSOI transistor degradation.
AbstractList	In this article, a doped fully depleted silicon on insulator (FDSOI) behavior for the 65-nm partially depleted silicon on insulator (PDSOI) technology is demonstrated to understand the output voltage shift of a voltage reference (VR) undergoing dose deposition in real time. From an in-depth top-bottom analysis, including both experiments and technology computer aided design (TCAD)/simulation program with integrated circuit emphasis (SPICE) simulations, we highlighted this unexpected doped FDSOI behavior. This study shows how it worsens the total ionizing dose (TID) effects due to the coupling effect between the front and back interfaces, not usual in this technology. A new threshold voltage model considering channel doping and TID is developed, showing how doping concentration is an important hardening parameter. This model is reused, in a multiscale approach, to reproduce the output voltage shift of a VR based on the PDSOI transistor degradation.
Author	Martinie, S. Bournel, A. Charbonnier, G. Marcandella, C. Lomonaco, J. Rostand, N. Bedecarrats, T.
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Cites_doi	10.1016/j.sse.2023.108813 10.1007/978-1-4419-9106-5 10.1016/j.sse.2019.05.005 10.1109/TNS.2023.3337288 10.1109/TNS.2013.2249095 10.1109/TNS.2014.2367512 10.1109/TED.2024.3363110 10.1109/TNS.2023.3252439 10.1016/j.microrel.2016.11.007 10.1016/j.sse.2018.08.011 10.1016/j.microrel.2023.115273 10.1109/TNS.2003.812927 10.1109/IEDM.2013.6724728 10.1109/TNS.2018.2828142 10.1109/TED.2015.2458339 10.1109/t-ed.1983.21282 10.1109/TCSI.2009.2028411 10.1016/j.microrel.2018.03.014 10.1109/TNS.2010.2104162 10.1109/TNS.2019.2911429 10.1109/TNS.2002.805387 10.1109/TNS.2003.812928 10.1007/978-90-481-8614-3
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SubjectTerms	CAD Circuits Computer aided design Degradation Depletion Doping Fully depleted silicon on insulator (FDSOI) Integrated circuit modeling Integrated circuits modeling Multiscale analysis partially depleted silicon on insulator (PDSOI) Photonic band gap Predictive models radiation experiments Semiconductor process modeling Silicon Silicon-on-insulator simulation program with integrated circuit emphasis (SPICE) simulation SOI (semiconductors) technology computer aided design (TCAD) Threshold voltage Total ionizing dose total ionizing dose (TID) Transistors Voltage voltage reference (VR)
Title	Modeling of Doped Fully Depleted Behavior Induced by Total Ionizing Dose in Voltage Reference Circuits From a 65-nm Partially Depleted SOI Technology
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