High Performance GCM Architecture for the Security of High Speed Network

Advanced Encryption Standard (AES) is an effective cryptography algorithm for providing the better data communication since it guaranties high security. The Galois/Counter Mode (AES-GCM) has been integrated in various security constrained applications because it provides both authentication and conf...

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Vydáno v:International journal of parallel programming Ročník 46; číslo 5; s. 904 - 922
Hlavní autoři: Mohanraj, Vanitha, Sakthivel, R., Paul, Anand, Rho, Seungmin
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York Springer US 01.10.2018
Springer Nature B.V
Témata:
Algorithms
CMOS
Computer programming
Computer Science
Cryptography
Encryption
Parallel processing
Processor Architectures
Software Engineering/Programming and Operating Systems
Special Issue on Parallel Approaches for Data Mining in the Internet of Things Realm
Theory of Computation
GHASH function
High performance
Advanced Encryption Standard
Galois/Counter Mode
Parallel architecture
ISSN:0885-7458, 1573-7640
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Shrnutí:Advanced Encryption Standard (AES) is an effective cryptography algorithm for providing the better data communication since it guaranties high security. The Galois/Counter Mode (AES-GCM) has been integrated in various security constrained applications because it provides both authentication and confidentiality. AES algorithm helps to provide data confidentiality while authentication is provided by a universal GHASH function. Since most of existing GCM architectures concentrated on power and area reduction but an compact and efficient hardware architecture should also be considered. In this paper, high-performance architecture for GCM is proposed and its implementation is described. In order to achieve higher operating frequency and throughput, pipelined S-boxes are used in AES algorithm. For a GCM realization of AES, a high-speed, high-throughput, parallel architecture is proposed. Experimental results proves that the performance of the proposed work is around 17% higher than the existing architecture with 3 Gb/s throughput using TSMC 45-nm CMOS technology.
Bibliografie:ObjectType-Article-1
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ISSN:0885-7458
1573-7640
DOI:10.1007/s10766-017-0545-7