SWG: an architecture for sparse weight gradient computation

On-device training for deep neural networks (DNN) has become a trend due to various user preferences and scenarios. The DNN training process consists of three phases, feedforward (FF), backpropagation (BP), and weight gradient (WG) update. WG takes about one-third of the computation in the whole tra...

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Vydáno v:	Science China. Information sciences Ročník 67; číslo 2; s. 122405
Hlavní autoři:	Wu, Weiwei, Tu, Fengbin, Li, Xiangyu, Wei, Shaojun, Yin, Shouyi
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	Beijing Science China Press 01.02.2024 Springer Nature B.V
Témata:	Artificial neural networks Back propagation networks Computer architecture Computer Science Feature maps Hardware Information Systems and Communication Service Optimization Research Paper Sparsity State of the art Training Workload Workloads CNN training sparsity gradient computation architecture
ISSN:	1674-733X, 1869-1919
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Abstract	On-device training for deep neural networks (DNN) has become a trend due to various user preferences and scenarios. The DNN training process consists of three phases, feedforward (FF), backpropagation (BP), and weight gradient (WG) update. WG takes about one-third of the computation in the whole training process. Current training accelerators usually ignore the special computation property of WG and process it in a way similar to FF/BP. Besides, the extensive data sparsity existing in WG, which brings opportunities to save computation, is not well explored. Nevertheless, exploiting the optimization opportunities would meet three underutilization problems, which are caused by (1) the mismatch between WG data dimensions and hardware parallelism, (2) the full sparsity, i.e., the sparsity of feature map (Fmap), error map (Emap), and gradient, and (3) the workload imbalance resulting from irregular sparsity. In this paper, we propose a specific architecture for sparse weight gradient (SWG) computation. The architecture is designed based on hierarchical unrolling and sparsity-aware (HUSA) dataflow to exploit the optimization opportunities of the special computation property and full data sparsity. In HUSA dataflow, the data dimensions are unrolled hierarchically on the hardware architecture. A valid-data trace (VDT) mechanism is embedded in the dataflow to avoid the underutilization caused by the two-sided input sparsity. The gradient is unrolled in PE to alleviate the underutilization induced by output sparsity while maintaining the data reuse opportunities. Besides, we design an intra- and inter-column balancer (IIBLC) to dynamically tackle the workload imbalance problem resulting from the irregular sparsity. Experimental results show that with HUSA dataflow exploiting the full sparsity, SWG achieves a speedup of 12.23× over state-of-the-art gradient computation architecture, TrainWare. SWG helps to improve the energy efficiency of the state-of-the-art training accelerator LNPU from 7.56 to 10.58 TOPS/W.
AbstractList	On-device training for deep neural networks (DNN) has become a trend due to various user preferences and scenarios. The DNN training process consists of three phases, feedforward (FF), backpropagation (BP), and weight gradient (WG) update. WG takes about one-third of the computation in the whole training process. Current training accelerators usually ignore the special computation property of WG and process it in a way similar to FF/BP. Besides, the extensive data sparsity existing in WG, which brings opportunities to save computation, is not well explored. Nevertheless, exploiting the optimization opportunities would meet three underutilization problems, which are caused by (1) the mismatch between WG data dimensions and hardware parallelism, (2) the full sparsity, i.e., the sparsity of feature map (Fmap), error map (Emap), and gradient, and (3) the workload imbalance resulting from irregular sparsity. In this paper, we propose a specific architecture for sparse weight gradient (SWG) computation. The architecture is designed based on hierarchical unrolling and sparsity-aware (HUSA) dataflow to exploit the optimization opportunities of the special computation property and full data sparsity. In HUSA dataflow, the data dimensions are unrolled hierarchically on the hardware architecture. A valid-data trace (VDT) mechanism is embedded in the dataflow to avoid the underutilization caused by the two-sided input sparsity. The gradient is unrolled in PE to alleviate the underutilization induced by output sparsity while maintaining the data reuse opportunities. Besides, we design an intra- and inter-column balancer (IIBLC) to dynamically tackle the workload imbalance problem resulting from the irregular sparsity. Experimental results show that with HUSA dataflow exploiting the full sparsity, SWG achieves a speedup of 12.23× over state-of-the-art gradient computation architecture, TrainWare. SWG helps to improve the energy efficiency of the state-of-the-art training accelerator LNPU from 7.56 to 10.58 TOPS/W.
ArticleNumber	122405
Author	Wei, Shaojun Yin, Shouyi Tu, Fengbin Li, Xiangyu Wu, Weiwei
Author_xml	– sequence: 1 givenname: Weiwei surname: Wu fullname: Wu, Weiwei organization: School of Integrated Circuits, Tsinghua University – sequence: 2 givenname: Fengbin surname: Tu fullname: Tu, Fengbin organization: Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology – sequence: 3 givenname: Xiangyu surname: Li fullname: Li, Xiangyu organization: School of Integrated Circuits, Tsinghua University – sequence: 4 givenname: Shaojun surname: Wei fullname: Wei, Shaojun organization: School of Integrated Circuits, Tsinghua University – sequence: 5 givenname: Shouyi surname: Yin fullname: Yin, Shouyi email: yinsy@tsinghua.edu.cn organization: School of Integrated Circuits, Tsinghua University
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SubjectTerms	Artificial neural networks Back propagation networks Computer architecture Computer Science Feature maps Hardware Information Systems and Communication Service Optimization Research Paper Sparsity State of the art Training Workload Workloads
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Title	SWG: an architecture for sparse weight gradient computation
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