A Concept of Visual Programming Tool for Learning VHDL

Due to the COVID-19 pandemic, distance education starts playing a crucial role in higher education and the need for development of educational tools, helping the students learn better at home cannot be ignored. Teaching programming languages online is a complicated task and when the course subject i...

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Veröffentlicht in:IOP conference series. Materials Science and Engineering Jg. 1031; H. 1; S. 12120 - 12126
1. Verfasser: Ivanova, Aneliya
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Bristol IOP Publishing 01.01.2021
Schlagworte:
CAI
Computer assisted instruction
COVID-19
Digital electronics
Distance learning
Hardware description languages
Logic design
Model testing
Students
Training
Visual programming languages
ISSN:1757-8981, 1757-899X
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Abstract Due to the COVID-19 pandemic, distance education starts playing a crucial role in higher education and the need for development of educational tools, helping the students learn better at home cannot be ignored. Teaching programming languages online is a complicated task and when the course subject is programmable logic design through Hardware Description Languages (HDLs), online teaching becomes a complex challenge. In this paper is presented a concept of a training environment that uses the visual programing technique to help the students create VHDL models of various digital devices. The students construct VHDL models by combining simple visual objects while the environment is providing guidance in real time and is preventing a wrong match of VHDL operators and signals. The strategy for building a model of a compex digital circuit by moving and connecting visual objects will help the students with visual kinaesthetic learning style to internalize the concept and the structure of the VHDL model. The training environment will benefit mostly the students, learning in distance mode, but it is also useful for face-to-face students, who find it difficult to assimilate the specifics of VHDL modelling.
AbstractList Due to the COVID-19 pandemic, distance education starts playing a crucial role in higher education and the need for development of educational tools, helping the students learn better at home cannot be ignored. Teaching programming languages online is a complicated task and when the course subject is programmable logic design through Hardware Description Languages (HDLs), online teaching becomes a complex challenge. In this paper is presented a concept of a training environment that uses the visual programing technique to help the students create VHDL models of various digital devices. The students construct VHDL models by combining simple visual objects while the environment is providing guidance in real time and is preventing a wrong match of VHDL operators and signals. The strategy for building a model of a compex digital circuit by moving and connecting visual objects will help the students with visual kinaesthetic learning style to internalize the concept and the structure of the VHDL model. The training environment will benefit mostly the students, learning in distance mode, but it is also useful for face-to-face students, who find it difficult to assimilate the specifics of VHDL modelling.
Author Ivanova, Aneliya
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  givenname: Aneliya
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  organization: University of Ruse, Faculty of Electrical Engineering, Electronics and Automation, Department of Computing , Bulgaria
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10.1016/j.jocs.2017.04.004
10.1007/s 11135-017-0509-4
10.4018/JCIT.2019010104
10.1109/ICETA.2016.7802048
10.1109/ICPC.2019.00028
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SubjectTerms CAI
Computer assisted instruction
COVID-19
Digital electronics
Distance learning
Hardware description languages
Logic design
Model testing
Students
Training
Visual programming languages
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