A new thread-level speculative automatic parallelization model and library based on duplicate code execution

Loop-efficient automatic parallelization has become increasingly relevant due to the growing number of cores in current processors and the programming effort needed to parallelize codes in these systems efficiently. However, automatic tools fail to extract all the available parallelism in irregular...

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Vydáno v:	The Journal of supercomputing Ročník 80; číslo 10; s. 13714 - 13737
Hlavní autoři:	Martínez, Millán A., Fraguela, Basilio B., Cabaleiro, José C., Rivera, Francisco F.
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	New York Springer US 01.07.2024 Springer Nature B.V
Témata:	C plus plus Compilers Computer Science Interpreters Libraries Processor Architectures Programming Languages Software User services Automatic parallelization Thread-level speculation Template metaprogramming Speculative parallelism
ISSN:	0920-8542, 1573-0484
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Abstract	Loop-efficient automatic parallelization has become increasingly relevant due to the growing number of cores in current processors and the programming effort needed to parallelize codes in these systems efficiently. However, automatic tools fail to extract all the available parallelism in irregular loops with indirections, race conditions or potential data dependency violations, among many other possible causes. One of the successful ways to automatically parallelize these loops is the use of speculative parallelization techniques. This paper presents a new model and the corresponding C++ library that supports the speculative automatic parallelization of loops in shared memory systems, seeking competitive performance and scalability while keeping user effort to a minimum. The primary speculative strategy consists of redundantly executing chunks of loop iterations in a duplicate fashion. Namely, each chunk is executed speculatively in parallel to obtain results as soon as possible and sequentially in a different thread to validate the speculative results. The implementation uses C++11 threads and it makes intensive use of templates and advanced multithreading techniques. An evaluation based on various benchmarks confirms that our proposal provides a competitive level of performance and scalability.
AbstractList	Loop-efficient automatic parallelization has become increasingly relevant due to the growing number of cores in current processors and the programming effort needed to parallelize codes in these systems efficiently. However, automatic tools fail to extract all the available parallelism in irregular loops with indirections, race conditions or potential data dependency violations, among many other possible causes. One of the successful ways to automatically parallelize these loops is the use of speculative parallelization techniques. This paper presents a new model and the corresponding C++ library that supports the speculative automatic parallelization of loops in shared memory systems, seeking competitive performance and scalability while keeping user effort to a minimum. The primary speculative strategy consists of redundantly executing chunks of loop iterations in a duplicate fashion. Namely, each chunk is executed speculatively in parallel to obtain results as soon as possible and sequentially in a different thread to validate the speculative results. The implementation uses C++11 threads and it makes intensive use of templates and advanced multithreading techniques. An evaluation based on various benchmarks confirms that our proposal provides a competitive level of performance and scalability.
Author	Fraguela, Basilio B. Rivera, Francisco F. Martínez, Millán A. Cabaleiro, José C.
Author_xml	– sequence: 1 givenname: Millán A. orcidid: 0000-0002-1442-7668 surname: Martínez fullname: Martínez, Millán A. email: millan.alvarez@udc.es organization: Universidade da Coruña, CITIC, Computer Architecture Group – sequence: 2 givenname: Basilio B. orcidid: 0000-0002-3438-5960 surname: Fraguela fullname: Fraguela, Basilio B. organization: Universidade da Coruña, CITIC, Computer Architecture Group – sequence: 3 givenname: José C. orcidid: 0000-0002-5674-5162 surname: Cabaleiro fullname: Cabaleiro, José C. organization: Centro Singular de Investigación en Tecnoloxías Intelixentes (CiTIUS), Dpto. Electrónica e Computación, Universidade de Santiago de Compostela – sequence: 4 givenname: Francisco F. orcidid: 0000-0002-6728-9350 surname: Rivera fullname: Rivera, Francisco F. organization: Centro Singular de Investigación en Tecnoloxías Intelixentes (CiTIUS), Dpto. Electrónica e Computación, Universidade de Santiago de Compostela
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Cites_doi	10.1007/s10766-009-0111-z 10.1145/1543135.1542496 10.1145/1064978.1065043 10.1145/223428.207148 10.1002/int.23062 10.1109/TPDS.2005.69 10.1109/TPDS.2015.2393870 10.1080/09720529.2021.1951435 10.1145/564883.564885 10.1109/IPDPS.2002.1015493 10.1145/1562164.1562188 10.1109/MICRO.2008.4771802 10.1109/CGO.2009.18 10.1109/MICRO.2001.991127 10.1109/MICRO.2002.1176241 10.1145/1273442.1250759 10.1109/SNPD.2019.8935751 10.1145/1542275.1542333 10.1109/MICRO.2005.13 10.1007/978-3-030-28596-8_17
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Title	A new thread-level speculative automatic parallelization model and library based on duplicate code execution
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