FIPLib: An Image Processing Library for FPGAs Using High-Level Synthesis

This paper investigates the use of High-Level Synthesis (HLS) for designing parallel hardware architectures on FPGAs. HLS compilers, like the one used in Vitis HLS, extract the available parallelism so the HLS languages should be thought as inherently parallel and should be programmed with the targe...

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Bibliographic Details
Published in:International journal of parallel programming Vol. 53; no. 2; p. 13
Main Authors: Palazzari, Paolo, Faltelli, Marco, Iannone, Francesco
Format: Journal Article
Language:English
Published: New York Springer US 01.04.2025
Springer Nature B.V
Subjects:
Algorithms
Computer Science
Field programmable gate arrays
High level synthesis
Image processing
Libraries
Power consumption
Processor Architectures
Software Engineering/Programming and Operating Systems
Theory of Computation
Parallel processing
High-level synthesis
Image processing
FPGA
ISSN:0885-7458, 1573-7640
Online Access:Get full text
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Summary:This paper investigates the use of High-Level Synthesis (HLS) for designing parallel hardware architectures on FPGAs. HLS compilers, like the one used in Vitis HLS, extract the available parallelism so the HLS languages should be thought as inherently parallel and should be programmed with the target parallel architecture in mind. We discuss how HLS facilitated the development of FIPLib, an image processing library for FPGAs, leveraging the streaming model. This library comprises parallel kernels connected through streams to implement a streaming data-flow computation. Following an overview of the library’s functionalities and its parallel implementation, we present the benefits of adopting this FPGA library, particularly in terms of speed and power consumption. We conduct a comparative analysis by implementing two image processing algorithms using both our FPGA library and the equivalent OpenCV CPU and GPU implementation. The results demonstrate that FPGAs programmed through FIPLib can significantly accelerate computations and/or reduce power consumption.
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ISSN:0885-7458
1573-7640
DOI:10.1007/s10766-025-00784-5