Systolic array design space exploration of interpolators for multi-rate systems

This study presents the development and comparison of interpolator systolic array designs and implementations. Systematic methodology was applied to the difference equations defining the interpolator algorithm. A dependence graph for the interpolator was obtained that combined the upsampler and the...

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Vydáno v:	IET circuits, devices & systems Ročník 13; číslo 7; s. 1032 - 1038
Hlavní autoři:	Shoukry, Mohammed, Gebali, Fayez, Agathoklis, Panajotis
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	Stevenage The Institution of Engineering and Technology 01.10.2019 John Wiley & Sons, Inc
Témata:	Algorithms anti-imaging filter conventional designs dependence graph Difference equations fastest design Field programmable gate arrays field-programmable gate array implementations Fourier transforms Gate arrays Hardware hardware implementation interpolation interpolator algorithm interpolator implementation interpolator systolic array designs multirate systems projection operations proposed designs Repeaters Research Article Scheduling Signal processing Space exploration systematic methodology systolic array design options systolic arrays field programmable gate arrays conventional designs systolic arrays interpolator algorithm anti-imaging filter systolic array design options field-programmable gate array implementations projection operations difference equations multirate systems interpolator implementation systematic methodology interpolation interpolator systolic array designs dependence graph proposed designs fastest design hardware implementation
ISSN:	1751-858X, 1751-8598, 1751-8598
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Popis
Shrnutí:	This study presents the development and comparison of interpolator systolic array designs and implementations. Systematic methodology was applied to the difference equations defining the interpolator algorithm. A dependence graph for the interpolator was obtained that combined the upsampler and the anti-imaging filter. Different data scheduling and projection operations were developed. Nine systolic array design options were obtained and evaluated. The fastest design was selected for hardware implementation. Field-programmable gate array implementations for the conventional and proposed designs confirm that the proposed interpolator implementation requires no more than 61.7% of the hardware resources required in the conventional design and are at least 63.9% faster than the conventional design.
Bibliografie:	ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14
ISSN:	1751-858X 1751-8598 1751-8598
DOI:	10.1049/iet-cds.2018.5491