Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing

This paper presents an evolvable hardware system, fully contained in an FPGA, which is capable of autonomously generating digital processing circuits, implemented on an array of processing elements (PEs). Candidate circuits are generated by an embedded evolutionary algorithm and implemented by means...

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Vydané v:	IEEE transactions on computers Ročník 62; číslo 8; s. 1481 - 1493
Hlavní autori:	Salvador, R., Otero, A., Mora, J., de la Torre, E., Riesgo, T., Sekanina, L.
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York IEEE 01.08.2013 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	adaptable architectures Adaptive systems Arrays autonomous systems Circuits Evolutionary computing evolutionary computing and genetic algorithms Evolvable hardware Filtering Filtration FPGAs Genetic algorithms Logic reconfigurable hardware Reconfiguration self-adaptive systems Self-organizing networks Studies
ISSN:	0018-9340, 1557-9956
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