DLBF: A low overhead wear leveling algorithm for embedded systems with hybrid memory - Niu, Na; Fu, Fangfa; Yang, Bing; Wang, Qiang; Yuan, Jiacai; Lai, Fengchang; Zhao, Xinyu; Zhang, Zhewen; Wang, Jinxiang (Microelectronics and reliability, 2021)
Due to its attractive characters, nanosecond ranged access latency and higher bit density，phase change memory (PCM) has emerged as a promising main memory candidate for embedded systems in the future. However, relatively lower endurance has limited its practical application. Discussions regarding hybrid memory wear leveling algorithms have dominated research dereliction in recent years. However, most previous wear leveling schemes could not predict the write and read hot pages accurately and always greatly depend on reference-count recording lists to predict the hot of the pages which would bring higher space overhead to the whole system. In this paper, we propose a novel hardware wear leveling algorithm named DLBF to solve the problems mentioned above. It simultaneously considers both page access frequencies with write/read counting bloom filters and memory access recency with dynamic changing write and read thresholds. The proposed algorithm requires only a small amount of space overhead by adopting write and read counting bloom filters. According to experiment results, DLBF evenly distributes write operations among the entire PCM memory space and extends hybrid system lifetime by 1.47 times and 1.46times while compared with bloom filter algorithm and SWL algorithm. Meanwhile, compared with previous algorithms, the proposed algorithm contributes to improving the PCM hit ratio and system bus utilization.