Edge-Based Heuristics for Optimizing Shortcut-Augmented Topologies for HPC Interconnects

Interconnection network topology is critical for the overall performance of HPC systems. While many regular and irregular topologies have been proposed in the past, recent work has shown the promise of shortcut-augmented topologies that offer multi-fold reduction in network diameter and hop count ov...

Celý popis

Uložené v:
Podrobná bibliografia
Vydané v:Electronics (Basel) Ročník 11; číslo 17; s. 2778
Hlavní autori: Fuad, Kazi Ahmed Asif, Zeng, Kai, Chen, Lizhong
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: Basel MDPI AG 01.09.2022
Predmet:
Algorithms
Analysis
Apexes
Graph theory
Heuristic
Heuristic methods
Heuristic programming
High performance computing
Network architecture
Network topologies
Reduction
Topology optimization
United States
ISSN:2079-9292, 2079-9292
On-line prístup:Získať plný text
Tagy: Pridať tag
Žiadne tagy, Buďte prvý, kto otaguje tento záznam!
Popis
Shrnutí:Interconnection network topology is critical for the overall performance of HPC systems. While many regular and irregular topologies have been proposed in the past, recent work has shown the promise of shortcut-augmented topologies that offer multi-fold reduction in network diameter and hop count over conventional topologies. However, the large number of possible shortcuts creates an enormous design space for this new type of topology, and existing approaches are extremely slow and do not find shortcuts that are globally optimal. In this paper, we propose an efficient heuristic approach, called EdgeCut, which generates high-quality shortcut-augmented topologies. EdgeCut can identify more globally useful shortcuts by making its considerations from the perspective of edges instead of vertices. An additional implementation is proposed that approximates the costly all-pair shortest paths calculation, thereby further speeding up the scheme. Quantitative comparisons over prior work show that the proposed approach achieves a 1982× reduction in search time while generating better or equivalent topologies in 94.9% of the evaluated cases.
Bibliografia:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ISSN:2079-9292
2079-9292
DOI:10.3390/electronics11172778