Reliable Concurrent Error Detection Architectures for Extended Euclidean-Based Division Over (2^)

The extended Euclidean algorithm (EEA) is an important scheme for performing the division operation in finite fields. Many sensitive and security-constrained applications such as those using the elliptic curve cryptography for establishing key agreement schemes, augmented encryption approaches, and...

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Vydáno v:IEEE transactions on very large scale integration (VLSI) systems Ročník 22; číslo 5; s. 995 - 1003
Hlavní autoři: Mozaffari-Kermani, Mehran, Azarderakhsh, Reza, Lee, Chiou-Yng, Bayat-Sarmadi, Siavash
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York IEEE 01.05.2014
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
Algorithms
Codes
Constraints
Cryptography
Digital signatures
Division
Efficient fault diagnosis
Elliptic curve cryptography
Encryption
Error correction & detection
error coverage (EC)
Error detection
extended Euclidean algorithm (EEA)
Fault diagnosis
Galois fields
Hardware
Mathematical analysis
Prediction algorithms
Predictive models
Reliability
reliable and constrained embedded systems
Very large scale integration
Efficient fault diagnosis
reliable and constrained embedded systems
extended Euclidean algorithm (EEA)
error coverage (EC)
ISSN:1063-8210, 1557-9999
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Popis
Shrnutí:The extended Euclidean algorithm (EEA) is an important scheme for performing the division operation in finite fields. Many sensitive and security-constrained applications such as those using the elliptic curve cryptography for establishing key agreement schemes, augmented encryption approaches, and digital signature algorithms utilize this operation in their structures. Although much study is performed to realize the EEA in hardware efficiently, research on its reliable implementations needs to be done to achieve fault-immune reliable structures. In this regard, this paper presents a new concurrent error detection (CED) scheme to provide reliability for the aforementioned sensitive and constrained applications. Our proposed CED architecture is a step forward toward more reliable architectures for the EEA algorithm architectures. Through simulations and based on the number of parity bits used, the error detection capability of our CED architecture is derived to be 100% for single-bit errors and close to 99% for the experimented multiple-bit errors. In addition, we present the performance degradations of the proposed approach, leading to low-cost and reliable EEA architectures. The proposed reliable architectures are also suitable for constrained and fault-sensitive embedded applications utilizing the EEA hardware implementations.
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ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2013.2260570