A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grøstl

One of the five final SHA-3 candidates, Grøstl, has been inspired by the Advanced Encryption Standard. This unique feature can be exploited in a large variety of practical applications. In order to have a better picture of the Grøstl–AES computational efficiency (high-level scheduling, internal pipe...

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Veröffentlicht in:Microprocessors and microsystems Jg. 37; H. 6-7; S. 572 - 582
Hauptverfasser: Rogawski, Marcin, Gaj, Kris, Homsirikamol, Ekawat
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Elsevier B.V 01.08.2013
Schlagworte:
AES
Grøstl
Hardware architectures
IPSec
Pipelining
Resource sharing
Scheduling
SHA-3 competition
IPSec
SHA-3 competition
Hardware architectures
Resource sharing
Scheduling
Pipelining
Grøstl
AES
ISSN:0141-9331, 1872-9436
Online-Zugang:Volltext
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Zusammenfassung:One of the five final SHA-3 candidates, Grøstl, has been inspired by the Advanced Encryption Standard. This unique feature can be exploited in a large variety of practical applications. In order to have a better picture of the Grøstl–AES computational efficiency (high-level scheduling, internal pipelining, resource sharing, etc.), we designed a high-speed coprocessor for the Grøstl-based HMAC and AES in the counter mode. This coprocessor offers high-speed computations of both authentication and encryption/decryption with relatively small penalty in terms of area and speed when compared to the authentication (original Grøstl circuitry) functionality only. From our perspective, the main advantage of Grøstl over other finalists is the fact that its hardware architecture naturally accommodates AES at the cost of a small area overhead.
ISSN:0141-9331
1872-9436
DOI:10.1016/j.micpro.2013.05.005