Rogawski, M., Gaj, K., & Homsirikamol, E. (2013). A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grøstl. Microprocessors and microsystems, 37(6-7), 572-582. https://doi.org/10.1016/j.micpro.2013.05.005
Citácia podle Chicago (17th ed.)Rogawski, Marcin, Kris Gaj, a Ekawat Homsirikamol. "A High-speed Unified Hardware Architecture for 128 and 256-bit Security Levels of AES and the SHA-3 Candidate Grøstl." Microprocessors and Microsystems 37, no. 6-7 (2013): 572-582. https://doi.org/10.1016/j.micpro.2013.05.005.
Citácia podľa MLA (8th ed.)Rogawski, Marcin, et al. "A High-speed Unified Hardware Architecture for 128 and 256-bit Security Levels of AES and the SHA-3 Candidate Grøstl." Microprocessors and Microsystems, vol. 37, no. 6-7, 2013, pp. 572-582, https://doi.org/10.1016/j.micpro.2013.05.005.