An embedded multi-core biometric identification system

Biometric identification systems exploit automated methods of recognition based on physiological or behavioural characteristics. Among these, fingerprints are very reliable as biometric identifiers. In order to build embedded systems performing real-time authentication, a fast computational unit for...

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Vydané v:Microprocessors and microsystems Ročník 35; číslo 5; s. 510 - 521
Hlavní autori: Danese, G., Giachero, M., Leporati, F., Nazzicari, N.
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: Elsevier B.V 01.07.2011
Predmet:
Algorithms implemented in hardware
Biometric authentication
Field programmable gate arrays
Multiple-processor systems
Real-time and embedded systems
Biometric authentication
Multiple-processor systems
Algorithms implemented in hardware
Real-time and embedded systems
Field programmable gate arrays
ISSN:0141-9331, 1872-9436
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Popis
Shrnutí:Biometric identification systems exploit automated methods of recognition based on physiological or behavioural characteristics. Among these, fingerprints are very reliable as biometric identifiers. In order to build embedded systems performing real-time authentication, a fast computational unit for image processing is required. In this paper we propose a parallel architecture that efficiently implements the high computationally demanding core of a matching algorithm based on Band-Limited Phase Only spatial Correlation (BLPOC), performed by two concurrent computational units implemented onto a Stratix II Altera family FPGA. The device here described is competitive with similar hardware solutions described in literature and outperforms the elaboration capabilities of general-purpose processors.
ISSN:0141-9331
1872-9436
DOI:10.1016/j.micpro.2011.03.003