Hardware-based spiking neural network architecture using simplified backpropagation algorithm and homeostasis functionality
Bio-inspired hardware-based spiking neural networks (SNNs) has been suggested as a promising computing system with low power consumption and parallel operation. We propose the supervised on-chip training method approximating the backpropagation algorithm and the pulse scheme applicable to the hardwa...
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| Veröffentlicht in: | Neurocomputing (Amsterdam) Jg. 428; S. 153 - 165 |
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| Sprache: | Englisch |
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Elsevier B.V
07.03.2021
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| ISSN: | 0925-2312, 1872-8286 |
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| Abstract | Bio-inspired hardware-based spiking neural networks (SNNs) has been suggested as a promising computing system with low power consumption and parallel operation. We propose the supervised on-chip training method approximating the backpropagation algorithm and the pulse scheme applicable to the hardware-based SNNs with the low memory dependency. The performance evaluation through the MNIST data set classification shows that the proposed system achieves a similar recognition rate compared to that of the software-based network. In addition, we also propose novel homeostasis functionality using bias synapse to achieve high performances. The homeostasis functionality well regulates the firing rate of the neurons and improves the recognition rate. The TFT-type flash memory cells are used as synaptic devices. A fully connected two-layer neural network with non-leaky integrate-and-fire (I&F) neurons is used in the simulation. We then investigate the effect of the variation of the hardware-based network on the recognition rate. The simulation results show that the proposed system is resistant to weight variation because on-chip training is adopted. |
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| AbstractList | Bio-inspired hardware-based spiking neural networks (SNNs) has been suggested as a promising computing system with low power consumption and parallel operation. We propose the supervised on-chip training method approximating the backpropagation algorithm and the pulse scheme applicable to the hardware-based SNNs with the low memory dependency. The performance evaluation through the MNIST data set classification shows that the proposed system achieves a similar recognition rate compared to that of the software-based network. In addition, we also propose novel homeostasis functionality using bias synapse to achieve high performances. The homeostasis functionality well regulates the firing rate of the neurons and improves the recognition rate. The TFT-type flash memory cells are used as synaptic devices. A fully connected two-layer neural network with non-leaky integrate-and-fire (I&F) neurons is used in the simulation. We then investigate the effect of the variation of the hardware-based network on the recognition rate. The simulation results show that the proposed system is resistant to weight variation because on-chip training is adopted. |
| Author | Park, Byung-Gook Kwon, Dongseok Lee, Soochang Woo, Sung Yun Bae, Jong-Ho Lee, Jong-Ho Kim, Jangsaeng Oh, Seongbin Kang, Won-Mook Kim, Chul-Heung |
| Author_xml | – sequence: 1 givenname: Jangsaeng surname: Kim fullname: Kim, Jangsaeng organization: Department of Electrical and Computer Engineering, Inter-University Semiconductor Research Center (ISRC), Seoul National University, Gwanak-ro, Gwanak-gu, Seoul 08826, Republic of Korea – sequence: 2 givenname: Dongseok surname: Kwon fullname: Kwon, Dongseok organization: Department of Electrical and Computer Engineering, Inter-University Semiconductor Research Center (ISRC), Seoul National University, Gwanak-ro, Gwanak-gu, Seoul 08826, Republic of Korea – sequence: 3 givenname: Sung Yun surname: Woo fullname: Woo, Sung Yun organization: Department of Electrical and Computer Engineering, Inter-University Semiconductor Research Center (ISRC), Seoul National University, Gwanak-ro, Gwanak-gu, Seoul 08826, Republic of Korea – sequence: 4 givenname: Won-Mook surname: Kang fullname: Kang, Won-Mook organization: Department of Electrical and Computer Engineering, Inter-University Semiconductor Research Center (ISRC), Seoul National University, Gwanak-ro, Gwanak-gu, Seoul 08826, Republic of Korea – sequence: 5 givenname: Soochang surname: Lee fullname: Lee, Soochang organization: Department of Electrical and Computer Engineering, Inter-University Semiconductor Research Center (ISRC), Seoul National University, Gwanak-ro, Gwanak-gu, Seoul 08826, Republic of Korea – sequence: 6 givenname: Seongbin surname: Oh fullname: Oh, Seongbin organization: Department of Electrical and Computer Engineering, Inter-University Semiconductor Research Center (ISRC), Seoul National University, Gwanak-ro, Gwanak-gu, Seoul 08826, Republic of Korea – sequence: 7 givenname: Chul-Heung surname: Kim fullname: Kim, Chul-Heung organization: Department of Electrical and Computer Engineering, Inter-University Semiconductor Research Center (ISRC), Seoul National University, Gwanak-ro, Gwanak-gu, Seoul 08826, Republic of Korea – sequence: 8 givenname: Jong-Ho surname: Bae fullname: Bae, Jong-Ho organization: Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720, USA – sequence: 9 givenname: Byung-Gook surname: Park fullname: Park, Byung-Gook organization: Department of Electrical and Computer Engineering, Inter-University Semiconductor Research Center (ISRC), Seoul National University, Gwanak-ro, Gwanak-gu, Seoul 08826, Republic of Korea – sequence: 10 givenname: Jong-Ho surname: Lee fullname: Lee, Jong-Ho email: jhl@snu.ac.kr organization: Department of Electrical and Computer Engineering, Inter-University Semiconductor Research Center (ISRC), Seoul National University, Gwanak-ro, Gwanak-gu, Seoul 08826, Republic of Korea |
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| Keywords | Homeostasis Hardware-based neural networks On-chip training Spiking Neural Networks (SNNs) Synaptic devices Supervised learning |
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