CMOS transconductance multipliers: a tutorial

Real time analog multiplication of two signals is one of the most important operations in analog signal processing. The multiplier is used not only as a computational building block but also as a programming element in systems such as filters, neural networks, and as mixers and modulators in a commu...

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Veröffentlicht in:IEEE transactions on circuits and systems. 2, Analog and digital signal processing Jg. 45; H. 12; S. 1550 - 1563
Hauptverfasser: Gunhee Han, Sanchez-Sinencio, E.
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York, NY IEEE 01.12.1998
Institute of Electrical and Electronics Engineers
Schlagworte:
Applied sciences
Bipolar transistor circuits
Circuit synthesis
Communication systems
Computer networks
Electronics
Exact sciences and technology
Filters
Integrated circuits
Integrated circuits by function (including memories and processors)
Modulation coding
Neural networks
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal processing
Transconductance
Tutorial
Circuit architecture
Polynomial function
Low voltage
Low noise circuit
Circuit design
Complementary MOS technology
Integrated circuit
Multiplier
Implementation
Transconductance
Bipolar transistor
ISSN:1057-7130
Online-Zugang:Volltext
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Zusammenfassung:Real time analog multiplication of two signals is one of the most important operations in analog signal processing. The multiplier is used not only as a computational building block but also as a programming element in systems such as filters, neural networks, and as mixers and modulators in a communication system. Although high performance bipolar junction transistor multipliers have been available for some time, the CMOS multiplier implementation is still a challenging subject especially for low-voltage and low-power circuit design. Despite the large number of papers proposing new CMOS multiplier structures, they can be roughly grouped into a few categories. This tutorial provides a complete survey of CMOS multipliers, presents a unified generation of multiplier architectures, and proposes the most recommended MOS multiplier structure. This tutorial could serve as a starting reference point (and metric) for comparison of new CMOS multiplier circuit configurations. An illustrative CMOS chip prototype verifying theoretical results is presented.
Bibliographie:ObjectType-Article-2
SourceType-Scholarly Journals-1
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ISSN:1057-7130
DOI:10.1109/82.746667