Eliminating interlocks in deeply pipelined processors by delay enforced multistreaming

The delay enforced multistreaming (DEMUS) processor architecture provides a simple, inexpensive ways of achieving high hardware utilization in deeply pipelined processors. Multiple streams share the pipeline in an interleaved fashion. Both the data dependency problem and the jump problem are prevent...

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Bibliographic Details
Published in:IEEE transactions on computers Vol. 40; no. 10; pp. 1125 - 1132
Main Author: McCrackin, D.C.
Format: Journal Article
Language:English
Published: IEEE 01.10.1991
Subjects:
Clocks
Computational modeling
Computer simulation
Counting circuits
Delay
Dispatching
Hardware
Pipeline processing
Registers
Throughput
ISSN:0018-9340
Online Access:Get full text
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Summary:The delay enforced multistreaming (DEMUS) processor architecture provides a simple, inexpensive ways of achieving high hardware utilization in deeply pipelined processors. Multiple streams share the pipeline in an interleaved fashion. Both the data dependency problem and the jump problem are prevented by enforcing enough interdispatch delay on each individual stream to prevent successive instructions from interfering with each other's execution. The structure and operation of a small DEMUS processor are presented, and four stream dispatching algorithms are compared by means of a simple simulation. Of the three implementable algorithms, the modified fixed delay (DEMUS/MFD) and encoded delay with fixed minimum (DEMUS/EDF) mechanisms yield the highest performance.< >
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ISSN:0018-9340
DOI:10.1109/12.93745