Eliminating interlocks in deeply pipelined processors by delay enforced multistreaming

The delay enforced multistreaming (DEMUS) processor architecture provides a simple, inexpensive ways of achieving high hardware utilization in deeply pipelined processors. Multiple streams share the pipeline in an interleaved fashion. Both the data dependency problem and the jump problem are prevent...

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Vydané v:	IEEE transactions on computers Ročník 40; číslo 10; s. 1125 - 1132
Hlavný autor:	McCrackin, D.C.
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	IEEE 01.10.1991
Predmet:	Clocks Computational modeling Computer simulation Counting circuits Delay Dispatching Hardware Pipeline processing Registers Throughput
ISSN:	0018-9340
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