Eliminating interlocks in deeply pipelined processors by delay enforced multistreaming

The delay enforced multistreaming (DEMUS) processor architecture provides a simple, inexpensive ways of achieving high hardware utilization in deeply pipelined processors. Multiple streams share the pipeline in an interleaved fashion. Both the data dependency problem and the jump problem are prevent...

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Vydáno v:IEEE transactions on computers Ročník 40; číslo 10; s. 1125 - 1132
Hlavní autor: McCrackin, D.C.
Médium: Journal Article
Jazyk:angličtina
Vydáno: IEEE 01.10.1991
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ISSN:0018-9340
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Abstract The delay enforced multistreaming (DEMUS) processor architecture provides a simple, inexpensive ways of achieving high hardware utilization in deeply pipelined processors. Multiple streams share the pipeline in an interleaved fashion. Both the data dependency problem and the jump problem are prevented by enforcing enough interdispatch delay on each individual stream to prevent successive instructions from interfering with each other's execution. The structure and operation of a small DEMUS processor are presented, and four stream dispatching algorithms are compared by means of a simple simulation. Of the three implementable algorithms, the modified fixed delay (DEMUS/MFD) and encoded delay with fixed minimum (DEMUS/EDF) mechanisms yield the highest performance.< >
AbstractList The delay enforced multistreaming (DEMUS) processor architecture provides a simple, inexpensive ways of achieving high hardware utilization in deeply pipelined processors. Multiple streams share the pipeline in an interleaved fashion. Both the data dependency problem and the jump problem are prevented by enforcing enough interdispatch delay on each individual stream to prevent successive instructions from interfering with each other's execution. The structure and operation of a small DEMUS processor are presented, and four stream dispatching algorithms are compared by means of a simple simulation. Of the three implementable algorithms, the modified fixed delay (DEMUS/MFD) and encoded delay with fixed minimum (DEMUS/EDF) mechanisms yield the highest performance.< >
The delay enforced multistreaming (DEMUS) processor architecture provides a simple, inexpensive ways of achieving high hardware utilization in deeply pipelined processors. Multiple streams share the pipeline in an interleaved fashion. Both the data dependency problem and the jump problem are prevented by enforcing enough interdispatch delay on each individual stream to prevent successive instructions from interfering with each other's execution. The structure and operation of a small DEMUS processor are presented, and four stream dispatching algorithms are compared by means of a simple simulation. Of the three implementable algorithms, the modified fixed delay (DEMUS/MFD) and encoded delay with fixed minimum (DEMUS/EDF) mechanisms yield the highest performance
The delay enforced multistreaming (DEMUS) processor architecture provides a simple, inexpensive way of achieving high hardware utilization in deeply pipelined processors. Multiple streams share the pipeline in an interleaved fashion. Both the data dependency problem and the jump problem are prevented by enforcing enough interdispatch delay on each individual stream to prevent successive instructions from interfering with each other's execution. The structure and operation of a small DEMUS processor are presented, and four stream dispatching algorithms are compared by means of a simple simulation. Of the three implementable algorithms, the modified fixed delay (DEMUS/MFD) and encoded delay with fixed minimum (DEMUS/EDF) mechanisms yield the highest performance. (I.E.)
Author McCrackin, D.C.
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Cites_doi 10.1109/2.68
10.1109/12.24291
10.1109/C-M.1972.216889
10.1147/rd.273.0237
10.1016/S0026-2692(88)80044-2
10.1145/30350.30384
10.1109/12.16503
10.1109/MC.1984.1658927
10.1109/MC.1982.1654133
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mccrackin (ref7) 1988
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SubjectTerms Clocks
Computational modeling
Computer simulation
Counting circuits
Delay
Dispatching
Hardware
Pipeline processing
Registers
Throughput
Title Eliminating interlocks in deeply pipelined processors by delay enforced multistreaming
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