On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplication

Lower-bound results on Boolean-function complexity under two different models are discussed. The first is an abstraction of tradeoffs between chip area and speed in very-large-scale-integrated (VLSI) circuits. The second is the ordered binary decision diagram (OBDD) representation used as a data str...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Veröffentlicht in:	IEEE transactions on computers Jg. 40; H. 2; S. 205 - 213
1. Verfasser:	Bryant, R.E.
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York, NY IEEE 01.02.1991 Institute of Electrical and Electronics Engineers
Schlagworte:	Applied sciences Boolean functions Chip scale packaging Computer science Data structures Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Input variables Integrated circuit technology Integrated circuits Logic circuits Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Size measurement Very large scale integration Lower bound Multiplication VLSI circuit Integrated circuit Boolean function Decision Complexity Diagram
ISSN:	0018-9340
Online-Zugang:	Volltext
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Schreiben Sie den ersten Kommentar!