Passive-Active Flowgraphs for Efficient Modeling and Design of Signal Processing Systems
In dataflow representations for signal processing systems, applications are represented as directed graphs in which vertices represent computations and edges correspond to buffers that store data as it passes among computations. The edges in the dataflow graph are single-input, single-output compone...
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| Veröffentlicht in: | Journal of signal processing systems Jg. 92; H. 10; S. 1133 - 1151 |
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| Abstract | In dataflow representations for signal processing systems, applications are represented as directed graphs in which vertices represent computations and edges correspond to buffers that store data as it passes among computations. The edges in the dataflow graph are single-input, single-output components that manage data transmission in a first-in, first-out (FIFO) fashion. In this paper, we formulate the vertices and edges into concepts called “active blocks” and “passive blocks”, respectively in the graph representation. Computation in the dataflow graph is represented as “active blocks”, while the concept of dataflow buffers is represented as “passive blocks”. Like dataflow edges, passive blocks are used to store data during the intervals between its production and consumption by actors. However, passive blocks can have multiple inputs and multiple outputs, and can incorporate operations on and rearrangements of the stored data subject to certain constraints. We define a form of flowgraph representation that is based on replacing dataflow edges with the proposed concept of passive blocks. We present a structured design methodology for utilizing this new form of signal processing flowgraph, and demonstrate its application to improving memory management efficiency, and execution time performance. |
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| AbstractList | In dataflow representations for signal processing systems, applications are represented as directed graphs in which vertices represent computations and edges correspond to buffers that store data as it passes among computations. The edges in the dataflow graph are single-input, single-output components that manage data transmission in a first-in, first-out (FIFO) fashion. In this paper, we formulate the vertices and edges into concepts called "active blocks" and "passive blocks", respectively in the graph representation. Computation in the dataflow graph is represented as "active blocks", while the concept of dataflow buffers is represented as "passive blocks". Like dataflow edges, passive blocks are used to store data during the intervals between its production and consumption by actors. However, passive blocks can have multiple inputs and multiple outputs, and can incorporate operations on and rearrangements of the stored data subject to certain constraints. We define a form of flowgraph representation that is based on replacing dataflow edges with the proposed concept of passive blocks. We present a structured design methodology for utilizing this new form of signal processing flowgraph, and demonstrate its application to improving memory management efficiency, and execution time performance. |
| Author | Lee, Yaesop Bhattacharyya, Shuvra S. Desnos, Karol Barford, Lee Liu, Yanzhou |
| Author_xml | – sequence: 1 givenname: Yaesop orcidid: 0000-0002-9293-4155 surname: Lee fullname: Lee, Yaesop email: yaesop@umd.edu organization: University of Maryland – sequence: 2 givenname: Yanzhou surname: Liu fullname: Liu, Yanzhou organization: University of Maryland – sequence: 3 givenname: Karol surname: Desnos fullname: Desnos, Karol organization: Univ Rennes, INSA Rennes, CNRS, IETR – UMR – sequence: 4 givenname: Lee surname: Barford fullname: Barford, Lee organization: Keysight Laboratories, Keysight Technologies Inc – sequence: 5 givenname: Shuvra S. surname: Bhattacharyya fullname: Bhattacharyya, Shuvra S. organization: University of Maryland, INSA/IETR/INRIA |
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| Issue | 10 |
| Keywords | Buffer management Signal processing systems Model-based design Dataflow |
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| References | BoutellierJErsfolkJLiliusJMattavelliMRoquierGSilvenOActor merging for dataflow process networksIEEE Transactions on Signal Processing2015631024962508334175210.1109/TSP.2015.2411229 Li, L., Sapio, A., Wu, J., Liu, Y., Lee, K., Wolf, M., & Bhattacharyya, S.S. (2017). Design and implementation of adaptive signal processing systems using Markov decision processes. In Proceedings of the International Conference on Application Specific Systems, Architectures, and Processors (pp. 170–175). Washington: Seattle. Liu, Y., Barford, L., & Bhattacharyya, S.S. (2015). Constant-rate clock recovery and jitter measurement on deep memory waveforms using dataflow. In Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, pp. 1590–1595. Bhattacharyya, S.S., Deprettere, E., & Leupers, R. (2019) In Takala, J. (Ed.), Handbook of Signal Processing Systems, 3rd edn. Berlin: Springer. Liu, Y., Barford, L., & Bhattacharyya, S.S. (2018). Generalized graph connections for dataflow modeling of DSP applications. In Proceedings of the IEEE Workshop on Signal Processing Systems (pp. 275–280). South Africa: Cape Town. Ha, S., Kim, S., Lee, C., Yi, Y., Kwon, S., & Joo, Y.P. (2007). PeaCE: A hardware-software codesign environment for multimedia embedded systems. ACM Transactions on Design Automation of Electronic Systems 12. Article No. 24. SchmogrowRError vector magnitude as a performance measure for advanced modulation formatsIEEE Photonics Technology Letters2012241616310.1109/LPT.2011.2172405 Stuijk, S., Geilen, M., & Basten, T. (2006). Exploring tradeoffs in buffer requirements and throughput constraints for synchronous dataflow graphs. In Proceedings of the Design Automation Conference. de Oliveira Castro, P., Louise, S., & Barthou, D. (2010). A multidimensional array slicing DSL for stream programming. In Proceedings of the International Conference on Complex, Intelligent and Software Intensive Systems, pp. 913–918. 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CudennecLDubrullePGaleaFGoubierTSirdeyRGenerating code and memory buffers to reorganize data on many-core architecturesProcedia Computer Science2014291123113310.1016/j.procs.2014.05.101 EkerJJanneckJWLeeEALiuJLiuXLudvigJNeuendorfferSSachsSXiongYTaming heterogeneity — the Ptolemy approachProceedings of the IEEE200391112714410.1109/JPROC.2002.805829 Sander, I. (2003). System modeling and design refinement in ForSyDe. Ph.D. thesis, Royal Institute of Technology, Sweden. Lee, E.A. (1991). Consistency in dataflow graphs IEEE Transactions on Parallel and Distributed Systems 2(2). Sung, W., Kim, J., & Ha, S. (1998). Memory efficient software synthesis from dataflow graph. In Proceedings of the International Symposium on System Synthesis, pp. 137–142. Benazouz, M., Marchetti, O., Munier-Kordon, A., & Urard, P. (2010). A new approach for minimizing buffer capacities with throughput constraint for embedded system design. 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| References_xml | – reference: BilsenGEngelsMLauwereinsRPeperstraeteJACyclo-static dataflowIEEE Transactions on Signal Processing199644239740810.1109/78.485935 – reference: OhHHaSFractional rate dataflow model and efficient code synthesis for multimedia applicationsACM SIGPLAN Notices200237415110.1145/566225.513834 – reference: Benazouz, M., Marchetti, O., Munier-Kordon, A., & Urard, P. (2010). A new approach for minimizing buffer capacities with throughput constraint for embedded system design. In Proceedings of the ACS/IEEE International Conference on Computer Systems and Applications, pp. 1–8. – reference: Bhattacharyya, S.S., Deprettere, E., & Leupers, R. (2019) In Takala, J. (Ed.), Handbook of Signal Processing Systems, 3rd edn. Berlin: Springer. – reference: MurthyPKBhattacharyyaSSBuffer merging — a powerful technique for reducing memory requirements of synchronous dataflow specificationsACM Transactions on Design Automation of Electronic Systems20049221223710.1145/989995.989999 – reference: Buck, J.T., & Lee, E.A. (1993). Scheduling dynamic dataflow graphs using the token flow model. In Proceedings of the International Conference on Acoustics, Speech, and Signal Processing. – reference: Desnos, K., Pelcat, M., Nezan, J.F., & Aridhi, S. (2016). On memory reuse between inputs and outputs of dataflow actors ACM Transactions on Embedded Computing Systems 15(2). – reference: Reekie, H.J. (1995). Realtime signal processing — dataflow, visual, and functional programming. Ph.D. thesis, University of Technology at Sydney. – reference: Lin, S., Liu, Y., Lee, K., Li, L., Plishker, W., & Bhattacharyya, S.S. (2017). The DSPCAD framework for modeling and synthesis of signal processing systems. In Ha, S., & Teich, J. (Eds.) handbook of hardware/software codesign, pp. 1–35. Springer. – reference: Liu, Y., Barford, L., & Bhattacharyya, S.S. (2015). Constant-rate clock recovery and jitter measurement on deep memory waveforms using dataflow. In Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, pp. 1590–1595. – reference: Tripakis, S., Bui, D., Geilen, M., Rodiers, B., & Lee, E.A. (2013). Compositionality in synchronous data flow: Modular code generation from hierarchical SDF graphs ACM Transactions on Embedded Computing Systems 12(3). – reference: Liu, Y., Barford, L., & Bhattacharyya, S.S. (2018). Generalized graph connections for dataflow modeling of DSP applications. In Proceedings of the IEEE Workshop on Signal Processing Systems (pp. 275–280). South Africa: Cape Town. – reference: Bhattacharyya, S.S., & Lee, E.A. (1992). Memory management for synchronous dataflow programs. Tech. Rep. UCB/ERL M92/128, Electronics Research Laboratory University of California at Berkeley. – reference: Buck, J.T. (1994). Static scheduling and code generation from dynamic dataflow graphs with integer-valued control streams. In Proceedings of the IEEE Asilomar Conference on Signals, Systems, and Computers, pp. 508–513. – reference: Lesparre, Y., Munier-Kordon, A., & Delosme, J.M. (2016). Evaluation of synchronous dataflow graph mappings onto distributed memory architectures. In Proceedings of the Euromicro Conference on Digital System Design, pp. 146–153. – reference: SchmogrowRError vector magnitude as a performance measure for advanced modulation formatsIEEE Photonics Technology Letters2012241616310.1109/LPT.2011.2172405 – reference: Stuijk, S., Geilen, M., & Basten, T. (2006). Exploring tradeoffs in buffer requirements and throughput constraints for synchronous dataflow graphs. In Proceedings of the Design Automation Conference. – reference: BoutellierJErsfolkJLiliusJMattavelliMRoquierGSilvenOActor merging for dataflow process networksIEEE Transactions on Signal Processing2015631024962508334175210.1109/TSP.2015.2411229 – reference: Ha, S., Kim, S., Lee, C., Yi, Y., Kwon, S., & Joo, Y.P. (2007). PeaCE: A hardware-software codesign environment for multimedia embedded systems. ACM Transactions on Design Automation of Electronic Systems 12. Article No. 24. – reference: Sander, I. (2003). System modeling and design refinement in ForSyDe. Ph.D. thesis, Royal Institute of Technology, Sweden. – reference: de Oliveira Castro, P., Louise, S., & Barthou, D. (2010). A multidimensional array slicing DSL for stream programming. In Proceedings of the International Conference on Complex, Intelligent and Software Intensive Systems, pp. 913–918. – reference: LeeEAMesserschmittDGSynchronous dataflowProceedings of the IEEE19877591235124510.1109/PROC.1987.13876 – reference: Fischaber, S., Woods, R., & McAllister, J. (2007). Soc memory hierarchy derivation from dataflow graphs. In Proceedings of the IEEE Workshop on Signal Processing Systems. – reference: Li, L., Sapio, A., Wu, J., Liu, Y., Lee, K., Wolf, M., & Bhattacharyya, S.S. (2017). Design and implementation of adaptive signal processing systems using Markov decision processes. In Proceedings of the International Conference on Application Specific Systems, Architectures, and Processors (pp. 170–175). Washington: Seattle. – reference: Ade, M., Lauwereins, R., & Peperstraete, J. (1997). Data memory minimisation for synchronous data flow graphs emulated on DSP-FPGA targets. In Proceedings of the Design Automation Conference, pp. 64–69. – reference: EkerJJanneckJWLeeEALiuJLiuXLudvigJNeuendorfferSSachsSXiongYTaming heterogeneity — the Ptolemy approachProceedings of the IEEE200391112714410.1109/JPROC.2002.805829 – reference: CudennecLDubrullePGaleaFGoubierTSirdeyRGenerating code and memory buffers to reorganize data on many-core architecturesProcedia Computer Science2014291123113310.1016/j.procs.2014.05.101 – reference: Lee, E.A. (1991). Consistency in dataflow graphs IEEE Transactions on Parallel and Distributed Systems 2(2). – reference: Pelcat, M., Piat, J., Wipliez, M., Aridhi, S., & Nezan, J.F. (2009). An open framework for rapid prototyping of signal processing applications. EURASIP Journal on Embedded Systems 2009. Article No. 11. – reference: LeeEAParksTMDataflow process networksProceedings of the IEEE199583577379910.1109/5.381846 – reference: Sung, W., Kim, J., & Ha, S. (1998). Memory efficient software synthesis from dataflow graph. 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| SubjectTerms | Apexes Buffers Circuits and Systems Computer Imaging Data transmission Electrical Engineering Engineering Engineering Sciences Graph representations Graph theory Graphical representations Image Processing and Computer Vision Memory management Pattern Recognition Pattern Recognition and Graphics Signal processing Signal,Image and Speech Processing Vision |
| Title | Passive-Active Flowgraphs for Efficient Modeling and Design of Signal Processing Systems |
| URI | https://link.springer.com/article/10.1007/s11265-020-01581-8 https://www.proquest.com/docview/2440368100 https://hal.science/hal-02956341 |
| Volume | 92 |
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