Design and application of multiscroll chaotic attractors based on memristors
A multi-segment nonlinear memristor model with controllable parameters is simplified significantly reducing circuit costs without compromising circuit performance. Different quantities of simplified memristor models are introduced into an improved Shimizu and Morioka (S-M) system, which constitute t...
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| Published in: | Integration (Amsterdam) Vol. 98; p. 102235 |
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| Main Authors: | , , , , |
| Format: | Journal Article |
| Language: | English |
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Elsevier B.V
01.09.2024
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| ISSN: | 0167-9260, 1872-7522 |
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| Abstract | A multi-segment nonlinear memristor model with controllable parameters is simplified significantly reducing circuit costs without compromising circuit performance. Different quantities of simplified memristor models are introduced into an improved Shimizu and Morioka (S-M) system, which constitute the one-directional memristive multiscroll chaotic attractor (1D-MMSCA) and the two-directional memristive multiscroll chaotic attractor (2D-MMSCA). Dynamical analysis is conducted from equilibrium points, Lyapunov exponents and bifurcation diagrams, Poincaré map, 0–1 tests, complexity, coexisting attractors, and National Institute of Standards and Technology (NIST) test. The Lyapunov exponents and bifurcation diagrams revealed that 1D-MMSCA exhibit rich dynamical behaviors, including fixed points, periodic orbits, transient quasi-periodic cycles, limit cycles, and period-doubling bifurcations. The 2D-MMSCA demonstrates simultaneous homogeneous and heterogeneous multi-stability and extreme multi-stability. Furthermore, an analog circuit is designed and simulated, and the results verify the circuit realizability and correctness of the MMSCAs. By utilizing an improved Euler algorithm and STM32 microcontroller, the implementation of MMSCAs are achieved, enhancing their applicability in the embedded systems domain. Finally, the drive-response synchronization constructed based on 1D-MMSCA exhibits a wide adjustable synchronization time, ranging from 49.3 s to 0.18 s. This significantly expands the application scope of the system. Additionally, a chaotic analog encrypted communication system has been developed using this synchronization framework. These advancements substantially enhance both the efficiency and practicality of the synchronization system.
•The paper simplifies a multi-segmented nonlinear memristor model with controllable parameters. This simplification leads to a more concise expression of equation and simpler circuit design.•By adjusting the parameters of the memristor, it becomes straightforward to obtain 2N+2(N=0,1,2⋯) chaotic attractors.•The 2D-MGMSCA simultaneously exhibits homogeneous and heterogeneous multi-stability and extreme multi-stability.•The drive-response synchronization constructed based on 1D-MMSCA exhibits a wide adjustable synchronization time, ranging from 49.3 s to 0.18 s. |
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| AbstractList | A multi-segment nonlinear memristor model with controllable parameters is simplified significantly reducing circuit costs without compromising circuit performance. Different quantities of simplified memristor models are introduced into an improved Shimizu and Morioka (S-M) system, which constitute the one-directional memristive multiscroll chaotic attractor (1D-MMSCA) and the two-directional memristive multiscroll chaotic attractor (2D-MMSCA). Dynamical analysis is conducted from equilibrium points, Lyapunov exponents and bifurcation diagrams, Poincaré map, 0–1 tests, complexity, coexisting attractors, and National Institute of Standards and Technology (NIST) test. The Lyapunov exponents and bifurcation diagrams revealed that 1D-MMSCA exhibit rich dynamical behaviors, including fixed points, periodic orbits, transient quasi-periodic cycles, limit cycles, and period-doubling bifurcations. The 2D-MMSCA demonstrates simultaneous homogeneous and heterogeneous multi-stability and extreme multi-stability. Furthermore, an analog circuit is designed and simulated, and the results verify the circuit realizability and correctness of the MMSCAs. By utilizing an improved Euler algorithm and STM32 microcontroller, the implementation of MMSCAs are achieved, enhancing their applicability in the embedded systems domain. Finally, the drive-response synchronization constructed based on 1D-MMSCA exhibits a wide adjustable synchronization time, ranging from 49.3 s to 0.18 s. This significantly expands the application scope of the system. Additionally, a chaotic analog encrypted communication system has been developed using this synchronization framework. These advancements substantially enhance both the efficiency and practicality of the synchronization system.
•The paper simplifies a multi-segmented nonlinear memristor model with controllable parameters. This simplification leads to a more concise expression of equation and simpler circuit design.•By adjusting the parameters of the memristor, it becomes straightforward to obtain 2N+2(N=0,1,2⋯) chaotic attractors.•The 2D-MGMSCA simultaneously exhibits homogeneous and heterogeneous multi-stability and extreme multi-stability.•The drive-response synchronization constructed based on 1D-MMSCA exhibits a wide adjustable synchronization time, ranging from 49.3 s to 0.18 s. |
| ArticleNumber | 102235 |
| Author | Cheng, Nana Zhang, Jie Lv, Jiliang Wei, Xiaodong Zuo, Jiangang |
| Author_xml | – sequence: 1 givenname: Jie surname: Zhang fullname: Zhang, Jie email: zhangjie@nwnu.edu.cn – sequence: 2 givenname: Xiaodong surname: Wei fullname: Wei, Xiaodong – sequence: 3 givenname: Jiangang surname: Zuo fullname: Zuo, Jiangang – sequence: 4 givenname: Nana surname: Cheng fullname: Cheng, Nana – sequence: 5 givenname: Jiliang surname: Lv fullname: Lv, Jiliang |
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| Cites_doi | 10.1175/1520-0469(1963)020<0130:DNF>2.0.CO;2 10.1007/s11071-018-04751-3 10.1016/j.ijnonlinmec.2019.07.013 10.1109/ACCESS.2022.3197790 10.1016/j.chaos.2023.113803 10.3390/electronics8111211 10.1016/j.chaos.2023.114440 10.1007/s12043-017-1493-x 10.1140/epjp/s13360-023-04558-1 10.1016/j.neunet.2023.12.008 10.1142/S0218127410027660 10.1016/j.chaos.2023.113837 10.1140/epjst/e2019-900035-y 10.1016/j.chaos.2021.111715 10.1142/S0217984922500804 10.3390/e25030495 10.1016/j.jare.2020.05.014 10.1109/TIE.2022.3225847 10.1016/j.chaos.2024.114676 10.1002/cta.2160 10.1142/S0218127402004164 10.1007/s00034-023-02573-2 10.1016/j.chaos.2006.04.058 10.1016/j.chaos.2023.113518 10.1088/1402-4896/ac379b 10.1016/j.chaos.2023.113341 10.1109/ACCESS.2024.3351693 10.1016/j.chaos.2022.112905 10.1109/TIE.2021.3099231 10.1016/j.chaos.2023.113228 10.1088/1402-4896/ace6db 10.1038/nature06932 10.1142/S0218127423500323 10.1016/j.chaos.2023.113619 10.1016/j.chaos.2023.114268 |
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| Keywords | Extreme multi-stability MMSCAs Homogeneous and heterogeneous multi-stability STM32 Circuit design Synchronization |
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