FPGA design and implementation for montgomery multiplication algorithm using MATLAB HDL coder - Elsayed, Ghada; Abass, Eman S. (Bulletin of the National Research Centre, 2024)
Background Modular multiplication for large numbers is especially important in cryptography algorithms such as RSA and elliptic curves. The Montgomery algorithm is the most famous and efficient one for calculating it. Hardware implementation for cryptography co-processors is better than software implementation in terms of speed and security. Many FPGA designs for the Montgomery multiplication algorithm was published based on hardware description languages like VERILOG and VHDL. This paper proposes the FPGA design and implementation using MATLAB HDL Coder. Results The algorithm is modified such that it can fit any small/large FPGA by introducing scaling factor. The design is configurable in both modulus length and the scaling factor. This paper performs a comparison between the synthesizing results for different scales and for different modulus lengths. The synthesizing is performed up to 8K bit modulus length, and it can be increased easily. In this paper, implementation of different modulus lengths with different frequencies and with different area utilization can be easily achieved. The design utilizes different area resources for each configuration. The target is xc7vx330t-2ffg1157 Virtex-7 Xilinx FPGA. The maximum frequency is 80.81 MHz for 4096-bit modulus length with 8-bit data width and 2 for serialization factor. The minimum area utilization is achieved for minimum configurations, i.e., 1024-bit modulus length with 8-bit data width and for unity serialization factor. Conclusions This paper proposes a scalable and configurable FPGA design for Montgomery multiplication co-processor-based HDL coder design.