APA (7th ed.) Citation

Elsayed, G., & Abass, E. S. (2024). FPGA design and implementation for montgomery multiplication algorithm using MATLAB HDL coder. Bulletin of the National Research Centre, 48(1), 129-16. https://doi.org/10.1186/s42269-024-01285-0

Chicago Style (17th ed.) Citation

Elsayed, Ghada, and Eman S. Abass. "FPGA Design and Implementation for Montgomery Multiplication Algorithm Using MATLAB HDL Coder." Bulletin of the National Research Centre 48, no. 1 (2024): 129-16. https://doi.org/10.1186/s42269-024-01285-0.

MLA (9th ed.) Citation

Elsayed, Ghada, and Eman S. Abass. "FPGA Design and Implementation for Montgomery Multiplication Algorithm Using MATLAB HDL Coder." Bulletin of the National Research Centre, vol. 48, no. 1, 2024, pp. 129-16, https://doi.org/10.1186/s42269-024-01285-0.