PaRSEC: Exploiting Heterogeneity to Enhance Scalability

New high-performance computing system designs with steeply escalating processor and core counts, burgeoning heterogeneity and accelerators, and increasingly unpredictable memory access times call for one or more dramatically new programming paradigms. These new approaches must react and adapt quickl...

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Vydáno v:Computing in science & engineering Ročník 15; číslo 6; s. 36 - 45
Hlavní autoři: Bosilca, George, Bouteiller, Aurelien, Danalis, Anthony, Faverge, Mathieu, Herault, Thomas, Dongarra, Jack J.
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York IEEE 01.11.2013
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
Adaptation models
Algorithms
Biological system modeling
Computation
Computational modeling
Computer architecture
distributed programming
Hardware
Heterogeneity
high-performance computing
HPC
Microprocessors
Parallel processing
Programming
programming paradigms
Runtime
Scalability
scheduling and task partitioning
scientific computing
Separation
Tasks
ISSN:1521-9615, 1558-366X
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Abstract New high-performance computing system designs with steeply escalating processor and core counts, burgeoning heterogeneity and accelerators, and increasingly unpredictable memory access times call for one or more dramatically new programming paradigms. These new approaches must react and adapt quickly to unexpected contentions and delays, and they must provide the execution environment with sufficient intelligence and flexibility to rearrange the execution to improve resource utilization. The authors present an approach based on task parallelism that reveals the application's parallelism by expressing its algorithm as a task flow. This strategy allows the algorithm to be decoupled from the data distribution and the underlying hardware, since the algorithm is entirely expressed as flows of data. This kind of layering provides a clear separation of concerns among architecture, algorithm, and data distribution. Developers benefit from this separation because they can focus solely on the algorithmic level without the constraints involved with programming for current and future hardware trends.
AbstractList New high-performance computing system designs with steeply escalating processor and core counts, burgeoning heterogeneity and accelerators, and increasingly unpredictable memory access times call for one or more dramatically new programming paradigms. These new approaches must react and adapt quickly to unexpected contentions and delays, and they must provide the execution environment with sufficient intelligence and flexibility to rearrange the execution to improve resource utilization. The authors present an approach based on task parallelism that reveals the application's parallelism by expressing its algorithm as a task flow. This strategy allows the algorithm to be decoupled from the data distribution and the underlying hardware, since the algorithm is entirely expressed as flows of data. This kind of layering provides a clear separation of concerns among architecture, algorithm, and data distribution. Developers benefit from this separation because they can focus solely on the algorithmic level without the constraints involved with programming for current and future hardware trends.
Author Danalis, Anthony
Bosilca, George
Bouteiller, Aurelien
Faverge, Mathieu
Dongarra, Jack J.
Herault, Thomas
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  organization: University of Tennessee
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Cites_doi 10.1177/1094342009106195
10.1142/S012962640100049X
10.1145/2185475.2185478
10.1109/PGEC.1966.264565
10.1109/ICPPW.2009.14
10.1002/cpe.1631
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SubjectTerms Adaptation models
Algorithms
Biological system modeling
Computation
Computational modeling
Computer architecture
distributed programming
Hardware
Heterogeneity
high-performance computing
HPC
Microprocessors
Parallel processing
Programming
programming paradigms
Runtime
Scalability
scheduling and task partitioning
scientific computing
Separation
Tasks
Title PaRSEC: Exploiting Heterogeneity to Enhance Scalability
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