Relaxed Min-Max Decoder Architectures for Nonbinary Low-Density Parity-Check Codes

Compared to binary low-density parity-check (LDPC) codes, nonbinary (NB) LDPC codes can achieve higher coding gain when the codeword length is moderate, but at the cost of higher decoding complexity. One major bottleneck of NB-LDPC decoding is the complicated check node processing. In this paper, a...

Full description

Saved in:

Bibliographic Details
Published in:	IEEE transactions on very large scale integration (VLSI) systems Vol. 21; no. 11; pp. 2010 - 2023
Main Authors:	Cai, Fang, Zhang, Xinmiao
Format:	Journal Article
Language:	English
Published:	New York, NY IEEE 01.11.2013 Institute of Electrical and Electronics Engineers
Subjects:	Algorithm design and analysis Applied sciences Check node processing Circuit properties Complexity theory Decoding Design. Technologies. Operation analysis. Testing Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Integrated circuits low-density parity-check codes min-max algorithm nonbinary Parity check codes partial-parallel Reliability Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal convertors VLSI design Performance evaluation Finite field partial-parallel VLSI circuit nonbinary Check node processing Coding circuit Integrated circuit design Decoding circuit Numerical method VLSI design Decoding Algorithm Implementation min-max algorithm Circuit architecture Finite element method Linear combination Coding Integrated circuit Parity check codes low-density parity-check codes Gain
ISSN:	1063-8210, 1557-9999
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!

Be the first to leave a comment!