Relaxed Min-Max Decoder Architectures for Nonbinary Low-Density Parity-Check Codes

Compared to binary low-density parity-check (LDPC) codes, nonbinary (NB) LDPC codes can achieve higher coding gain when the codeword length is moderate, but at the cost of higher decoding complexity. One major bottleneck of NB-LDPC decoding is the complicated check node processing. In this paper, a...

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Vydané v:IEEE transactions on very large scale integration (VLSI) systems Ročník 21; číslo 11; s. 2010 - 2023
Hlavní autori: Cai, Fang, Zhang, Xinmiao
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: New York, NY IEEE 01.11.2013
Institute of Electrical and Electronics Engineers
Predmet:
Algorithm design and analysis
Applied sciences
Check node processing
Circuit properties
Complexity theory
Decoding
Design. Technologies. Operation analysis. Testing
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Integrated circuits
low-density parity-check codes
min-max algorithm
nonbinary
Parity check codes
partial-parallel
Reliability
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal convertors
VLSI design
Performance evaluation
Finite field
partial-parallel
VLSI circuit
nonbinary
Check node processing
Coding circuit
Integrated circuit design
Decoding circuit
Numerical method
VLSI design
Decoding
Algorithm
Implementation
min-max algorithm
Circuit architecture
Finite element method
Linear combination
Coding
Integrated circuit
Parity check codes
low-density parity-check codes
Gain
ISSN:1063-8210, 1557-9999
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Popis
Shrnutí:Compared to binary low-density parity-check (LDPC) codes, nonbinary (NB) LDPC codes can achieve higher coding gain when the codeword length is moderate, but at the cost of higher decoding complexity. One major bottleneck of NB-LDPC decoding is the complicated check node processing. In this paper, a novel relaxed check node processing scheme is proposed for the min-max NB-LDPC decoding algorithm. Each finite field element of GF(2 p ) can be uniquely represented by a linear combination of p independent field elements. Making use of this property, an innovative method is developed in this paper to first find a set of the p most reliable variable-to-check messages with independent field elements, called the minimum basis. Then, the check-to-variable messages are efficiently computed from the minimum basis. With very small performance loss, the complexity of the check node processing can be substantially reduced using the proposed scheme. In addition, efficient VLSI architectures are developed to implement the proposed check node processing and the overall NB-LDPC decoder. Compared to the most efficient prior design, the proposed decoder for a (837, 726) NB-LDPC code over GF(2 5 ) can achieve 52% higher efficiency in terms of throughput-over-area ratio.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2012.2226920