APA (7th ed.) Citation

Cai, F., & Zhang, X. (2013). Relaxed Min-Max Decoder Architectures for Nonbinary Low-Density Parity-Check Codes. IEEE transactions on very large scale integration (VLSI) systems, 21(11), 2010-2023. https://doi.org/10.1109/TVLSI.2012.2226920

Chicago Style (17th ed.) Citation

Cai, Fang, and Xinmiao Zhang. "Relaxed Min-Max Decoder Architectures for Nonbinary Low-Density Parity-Check Codes." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, no. 11 (2013): 2010-2023. https://doi.org/10.1109/TVLSI.2012.2226920.

MLA (9th ed.) Citation

Cai, Fang, and Xinmiao Zhang. "Relaxed Min-Max Decoder Architectures for Nonbinary Low-Density Parity-Check Codes." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 11, 2013, pp. 2010-2023, https://doi.org/10.1109/TVLSI.2012.2226920.