Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies

A soft-error-immune quadruple-node-upset tolerant latch (SEI-QNUTL) with a low delay and high performance is proposed using 65-nm CMOS technology. The proposed SEI-QNUTL design consists of three soft-error-immune static random access memory (SEI-SRAM) cells. Furthermore, each SEI-SRAM cell employs p...

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Veröffentlicht in:IEEE transactions on very large scale integration (VLSI) systems Jg. 32; H. 4; S. 597 - 608
Hauptverfasser: Hao, Licai, Zhang, Xinyi, Dai, Chenghu, Zhao, Qiang, Lu, Wenjuan, Peng, Chunyu, Zhou, Yongliang, Lin, Zhiting, Wu, Xiulong
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.04.2024
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Algorithms
Data storage
Delay
Delays
High performance
high reliability
Latches
MOSFET
Nodes
polarity design technology
Power consumption
quadruple-node-upset (QNU)
Random access memory
Reliability
Reliability engineering
Robustness
Safety critical
Soft errors
source-isolation technology
Static random access memory
Transistors
Voltage
ISSN:1063-8210, 1557-9999
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Zusammenfassung:A soft-error-immune quadruple-node-upset tolerant latch (SEI-QNUTL) with a low delay and high performance is proposed using 65-nm CMOS technology. The proposed SEI-QNUTL design consists of three soft-error-immune static random access memory (SEI-SRAM) cells. Furthermore, each SEI-SRAM cell employs polarity design and source-isolation technology to reduce the number of sensitive nodes and enhance the reliability of the latch. Compared with state-of-the-art quadruple-node-upset (QNU) tolerant latches [including high-performance and low-cost single-event multiple-node-upsets resilient (HLMR), QNU tolerant latch (QNUTL), and Latch Design and Algorithm-based Verification Protected against Multiple-Node-Upsets (LDAVPM)], the proposed SEI-QNUTL design reduces (on average) the area, delay, and area-power-delay-product (APDP) by 47.0%, 25.0%, 46.5%, and 66.3%, respectively. Extensive variation analysis validates that the SEI-QNUTL design is less sensitive to process, voltage, and temperature (PVT) variations regarding power consumption and delay. Furthermore, Monte Carlo (MC) simulations show that the proposed latch exhibits high reliability when performing data storage. Compared with the existing latches, the SEI-QNUTL design makes a good tradeoff among delay, power, and area, and it can thus be used in safety-critical applications.
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ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2023.3342982