Hao, L., Zhang, X., Dai, C., Zhao, Q., Lu, W., Peng, C., . . . Wu, X. (2024). Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies. IEEE transactions on very large scale integration (VLSI) systems, 32(4), 597-608. https://doi.org/10.1109/TVLSI.2023.3342982
Citace podle Chicago (17th ed.)Hao, Licai, Xinyi Zhang, Chenghu Dai, Qiang Zhao, Wenjuan Lu, Chunyu Peng, Yongliang Zhou, Zhiting Lin, a Xiulong Wu. "Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 32, no. 4 (2024): 597-608. https://doi.org/10.1109/TVLSI.2023.3342982.
Citace podle MLA (9th ed.)Hao, Licai, et al. "Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 32, no. 4, 2024, pp. 597-608, https://doi.org/10.1109/TVLSI.2023.3342982.