Design of a square-root architecture: digit-serial approach
A new digit-serial square-root architecture based on radix-2 n arithmetic is presented. First, the conventional binary square-root algorithm is modified to a digit-serial algorithm which is used to design the proposed architecture. This architecture consists of a number of/i-bit controlled add/subtr...
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| Published in: | International journal of electronics Vol. 76; no. 1; pp. 15 - 25 |
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| Main Authors: | , |
| Format: | Journal Article |
| Language: | English |
| Published: |
Taylor & Francis Group
01.01.1994
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| ISSN: | 0020-7217, 1362-3060 |
| Online Access: | Get full text |
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| Summary: | A new digit-serial square-root architecture based on radix-2
n
arithmetic is presented. First, the conventional binary square-root algorithm is modified to a digit-serial algorithm which is used to design the proposed architecture. This architecture consists of a number of/i-bit controlled add/subtract (CAS) cells. We present two CAS cell architectures. The first is based on the conventional carry feed-back digit serial adder. The second is based on the carry feed-forward adder structure which results in the first reported square-root architecture that can be pipelined down to the bit-level. Furthermore, there is no specification of the type of adder used in the CAS cell. It can be a carry look-ahead or a carry propagate adder. The proposed architecture is general for any digit size and any wordlength. |
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| ISSN: | 0020-7217 1362-3060 |
| DOI: | 10.1080/00207219408925902 |