Design of a square-root architecture: digit-serial approach

A new digit-serial square-root architecture based on radix-2 n arithmetic is presented. First, the conventional binary square-root algorithm is modified to a digit-serial algorithm which is used to design the proposed architecture. This architecture consists of a number of/i-bit controlled add/subtr...

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Published in:International journal of electronics Vol. 76; no. 1; pp. 15 - 25
Main Authors: BASHAGHA, A. E., IBRAHIM, M. K.
Format: Journal Article
Language:English
Published: Taylor & Francis Group 01.01.1994
ISSN:0020-7217, 1362-3060
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Abstract A new digit-serial square-root architecture based on radix-2 n arithmetic is presented. First, the conventional binary square-root algorithm is modified to a digit-serial algorithm which is used to design the proposed architecture. This architecture consists of a number of/i-bit controlled add/subtract (CAS) cells. We present two CAS cell architectures. The first is based on the conventional carry feed-back digit serial adder. The second is based on the carry feed-forward adder structure which results in the first reported square-root architecture that can be pipelined down to the bit-level. Furthermore, there is no specification of the type of adder used in the CAS cell. It can be a carry look-ahead or a carry propagate adder. The proposed architecture is general for any digit size and any wordlength.
AbstractList A new digit-serial square-root architecture based on radix-2 n arithmetic is presented. First, the conventional binary square-root algorithm is modified to a digit-serial algorithm which is used to design the proposed architecture. This architecture consists of a number of/i-bit controlled add/subtract (CAS) cells. We present two CAS cell architectures. The first is based on the conventional carry feed-back digit serial adder. The second is based on the carry feed-forward adder structure which results in the first reported square-root architecture that can be pipelined down to the bit-level. Furthermore, there is no specification of the type of adder used in the CAS cell. It can be a carry look-ahead or a carry propagate adder. The proposed architecture is general for any digit size and any wordlength.
Author BASHAGHA, A. E.
IBRAHIM, M. K.
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References HARTLEY R I. (CIT0004) 1990; 37
PARHI K. K. (CIT0007) 1991; 38
BASHAGHA A. E. (CIT0002) 1993; 75
ERCEGOVAC M. D. (CIT0003) 1978
HWANG K. (CIT0005) 1979
IBRAHIM M. K. (CIT0006) 1993; 140
AGGOUN A. (CIT0001) 1993; 29
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Snippet A new digit-serial square-root architecture based on radix-2 n arithmetic is presented. First, the conventional binary square-root algorithm is modified to a...
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Title Design of a square-root architecture: digit-serial approach
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