An Efficient Training Accelerator for Transformers With Hardware-Algorithm Co-Optimization

Transformers have achieved significant success in deep learning, and training Transformers efficiently on resource-constrained platforms has been attracting continuous attention for domain adaptions and privacy concerns. However, deploying Transformers training on these platforms is still challengin...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems Jg. 31; H. 11; S. 1788 - 1801
Hauptverfasser:	Shao, Haikuo, Lu, Jinming, Wang, Meiqi, Wang, Zhongfeng
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.11.2023 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Algorithm-hardware codesign Algorithms Computational modeling Computer architecture Computer memory Data models Energy efficiency general matrix multiplication (GEMM) Hardware Memory management nonlinear function Optimization Platforms Task analysis Technology assessment Training training accelerator Transformer Transformers
ISSN:	1063-8210, 1557-9999
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Abstract	Transformers have achieved significant success in deep learning, and training Transformers efficiently on resource-constrained platforms has been attracting continuous attention for domain adaptions and privacy concerns. However, deploying Transformers training on these platforms is still challenging due to its dynamic workloads, intensive computations, and massive memory accesses. To address these issues, we propose an Efficient Training Accelerator for TRansformers (TRETA) through a hardware-algorithm co-optimization strategy. First, a hardware-friendly mixed-precision training algorithm is presented based on a compact and efficient data format, which significantly reduces the computation and memory requirements. Second, a flexible and scalable architecture is proposed to achieve high utilization of computing resources when processing arbitrary irregular general matrix multiplication (GEMM) operations during training. These irregular GEMMs lead to severe under-utilization when simply mapped on traditional systolic architectures. Third, we develop training-oriented architectures for the crucial Softmax and layer normalization functions in Transformers, respectively. These area-efficient modules have unified and flexible microarchitectures to meet various computation requirements of different training phases. Finally, TRETA is implemented under Taiwan Semiconductor Manufacturing Company (TSMC) 28-nm technology and evaluated on multiple benchmarks. The experimental results show that our training framework achieves the same accuracy as the full precision baseline. Moreover, TRETA can achieve 14.71 tera operations per second (TOPS) and 3.31 TOPS/W in terms of throughput and energy efficiency, respectively. Compared with prior arts, the proposed design shows 1.4-<inline-formula> <tex-math notation="LaTeX">24.5\times </tex-math></inline-formula> speedup and 1.5-<inline-formula> <tex-math notation="LaTeX">25.4\times </tex-math></inline-formula> energy efficiency improvement.
AbstractList	Transformers have achieved significant success in deep learning, and training Transformers efficiently on resource-constrained platforms has been attracting continuous attention for domain adaptions and privacy concerns. However, deploying Transformers training on these platforms is still challenging due to its dynamic workloads, intensive computations, and massive memory accesses. To address these issues, we propose an Efficient Training Accelerator for TRansformers (TRETA) through a hardware-algorithm co-optimization strategy. First, a hardware-friendly mixed-precision training algorithm is presented based on a compact and efficient data format, which significantly reduces the computation and memory requirements. Second, a flexible and scalable architecture is proposed to achieve high utilization of computing resources when processing arbitrary irregular general matrix multiplication (GEMM) operations during training. These irregular GEMMs lead to severe under-utilization when simply mapped on traditional systolic architectures. Third, we develop training-oriented architectures for the crucial Softmax and layer normalization functions in Transformers, respectively. These area-efficient modules have unified and flexible microarchitectures to meet various computation requirements of different training phases. Finally, TRETA is implemented under Taiwan Semiconductor Manufacturing Company (TSMC) 28-nm technology and evaluated on multiple benchmarks. The experimental results show that our training framework achieves the same accuracy as the full precision baseline. Moreover, TRETA can achieve 14.71 tera operations per second (TOPS) and 3.31 TOPS/W in terms of throughput and energy efficiency, respectively. Compared with prior arts, the proposed design shows 1.4–[Formula Omitted] speedup and 1.5–[Formula Omitted] energy efficiency improvement. Transformers have achieved significant success in deep learning, and training Transformers efficiently on resource-constrained platforms has been attracting continuous attention for domain adaptions and privacy concerns. However, deploying Transformers training on these platforms is still challenging due to its dynamic workloads, intensive computations, and massive memory accesses. To address these issues, we propose an Efficient Training Accelerator for TRansformers (TRETA) through a hardware-algorithm co-optimization strategy. First, a hardware-friendly mixed-precision training algorithm is presented based on a compact and efficient data format, which significantly reduces the computation and memory requirements. Second, a flexible and scalable architecture is proposed to achieve high utilization of computing resources when processing arbitrary irregular general matrix multiplication (GEMM) operations during training. These irregular GEMMs lead to severe under-utilization when simply mapped on traditional systolic architectures. Third, we develop training-oriented architectures for the crucial Softmax and layer normalization functions in Transformers, respectively. These area-efficient modules have unified and flexible microarchitectures to meet various computation requirements of different training phases. Finally, TRETA is implemented under Taiwan Semiconductor Manufacturing Company (TSMC) 28-nm technology and evaluated on multiple benchmarks. The experimental results show that our training framework achieves the same accuracy as the full precision baseline. Moreover, TRETA can achieve 14.71 tera operations per second (TOPS) and 3.31 TOPS/W in terms of throughput and energy efficiency, respectively. Compared with prior arts, the proposed design shows 1.4-<inline-formula> <tex-math notation="LaTeX">24.5\times </tex-math></inline-formula> speedup and 1.5-<inline-formula> <tex-math notation="LaTeX">25.4\times </tex-math></inline-formula> energy efficiency improvement.
Author	Wang, Zhongfeng Wang, Meiqi Shao, Haikuo Lu, Jinming
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Cites_doi	10.1109/TCSI.2020.3021397 10.1109/JSSC.2023.3234893 10.1109/CVPR42600.2020.00807 10.1109/CVPR.2016.90 10.1609/aaai.v35i4.16462 10.1109/HPCA47549.2020.00015 10.18653/v1/W18-6313 10.1109/TPDS.2022.3149787 10.1109/VLSIC.2018.8502276 10.1109/ISPASS48437.2020.00016 10.1109/ISSCC.2019.8662302 10.1007/s11263-021-01453-z 10.1109/CVPR42600.2020.00204 10.1109/JSSC.2021.3120113 10.1109/5.726791 10.1145/3079856.3080246 10.1109/ICASSP39728.2021.9413535 10.1109/ICCV48922.2021.00986 10.1109/CVPR.2009.5206848 10.1109/VLSICircuits18222.2020.9162917 10.21236/ADA273556 10.1109/ISCA52012.2021.00061 10.1109/ICASSP.2018.8462506 10.1109/OJSSCS.2021.3119554
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References	ref35 ref12 ref34 ref15 ref37 ref36 ref33 wang (ref22) 2022; 65 ref10 lan (ref4) 2019 radford (ref5) 2019; 1 ref39 ref19 ref18 han (ref16) 2015 nagel (ref17) 2021 parmar (ref8) 2018 ref24 ref45 ref26 ref25 ref20 brown (ref14) 2020 ref41 micikevicius (ref23) 2017 ref21 lu (ref30) 2022 liu (ref3) 2019 ref28 ref27 devlin (ref2) 2019; abs 1810 ref29 drumond (ref31) 2018 ref7 noh (ref38) 2022 ref9 dosovitskiy (ref6) 2020 vaswani (ref1) 2017 krizhevsky (ref44) 2009 huang (ref11) 2018 radford (ref13) 2018 kalamkar (ref32) 2019 ref40 merity (ref42) 2016 hill (ref43) 2015
References_xml	– ident: ref20 doi: 10.1109/TCSI.2020.3021397 – year: 2018 ident: ref11 article-title: Music transformer publication-title: arXiv 1809 04281 – ident: ref21 doi: 10.1109/JSSC.2023.3234893 – ident: ref19 doi: 10.1109/CVPR42600.2020.00807 – year: 2009 ident: ref44 publication-title: Learning multiple layers of features from tiny images – ident: ref15 doi: 10.1109/CVPR.2016.90 – year: 2022 ident: ref30 article-title: ETA: An efficient training accelerator for DNNs based on hardware-algorithm co-optimization publication-title: IEEE Trans Neural Netw Learn Syst – ident: ref33 doi: 10.1609/aaai.v35i4.16462 – year: 2019 ident: ref4 article-title: ALBERT: A lite BERT for self-supervised learning of language representations publication-title: arXiv 1909 11942 – ident: ref36 doi: 10.1109/HPCA47549.2020.00015 – ident: ref39 doi: 10.18653/v1/W18-6313 – year: 2015 ident: ref43 article-title: The Goldilocks principle: Reading children's books with explicit memory representations publication-title: arXiv 1511 02301 – ident: ref27 doi: 10.1109/TPDS.2022.3149787 – ident: ref25 doi: 10.1109/VLSIC.2018.8502276 – ident: ref40 doi: 10.1109/ISPASS48437.2020.00016 – ident: ref26 doi: 10.1109/ISSCC.2019.8662302 – ident: ref18 doi: 10.1007/s11263-021-01453-z – ident: ref24 doi: 10.1109/CVPR42600.2020.00204 – ident: ref35 doi: 10.1109/JSSC.2021.3120113 – year: 2020 ident: ref14 article-title: Language models are few-shot learners publication-title: arXiv 2005 14165 – start-page: 1 year: 2018 ident: ref31 article-title: Training DNNs with hybrid block floating point publication-title: Proc Adv Neural Inf Process Syst – year: 2018 ident: ref13 publication-title: Improving language understanding by generative pre-training – ident: ref29 doi: 10.1109/5.726791 – volume: abs 1810 year: 2019 ident: ref2 article-title: BERT: Pre-training of deep bidirectional transformers for language understanding publication-title: ArXiv – ident: ref28 doi: 10.1145/3079856.3080246 – year: 2019 ident: ref3 article-title: RoBERTa: A robustly optimized BERT pretraining approach publication-title: arXiv 1907 11692 – ident: ref10 doi: 10.1109/ICASSP39728.2021.9413535 – ident: ref7 doi: 10.1109/ICCV48922.2021.00986 – year: 2020 ident: ref6 article-title: An image is worth 16×16 words: Transformers for image recognition at scale publication-title: arXiv 2010 11929 – ident: ref45 doi: 10.1109/CVPR.2009.5206848 – year: 2021 ident: ref17 article-title: A white paper on neural network quantization publication-title: arXiv 2106 08295 – volume: 65 start-page: 1 year: 2022 ident: ref22 article-title: A 28 nm 27.5TOPS/W approximate-computing-based transformer processor with asymptotic sparsity speculating and out-of-order computing publication-title: IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers – year: 2022 ident: ref38 article-title: FlexBlock: A flexible DNN training accelerator with multi-mode block floating point support publication-title: arXiv 2203 06673 – start-page: 1 year: 2015 ident: ref16 article-title: Deep compression: Compressing deep neural network with pruning, trained quantization and Huffman coding publication-title: Proc Int Conf Learn Represent – year: 2019 ident: ref32 article-title: A study of BFLOAT16 for deep learning training publication-title: arXiv 1905 12322 – ident: ref34 doi: 10.1109/VLSICircuits18222.2020.9162917 – ident: ref41 doi: 10.21236/ADA273556 – year: 2017 ident: ref1 article-title: Attention is all you need publication-title: Proc NIPS – ident: ref37 doi: 10.1109/ISCA52012.2021.00061 – year: 2016 ident: ref42 article-title: Pointer sentinel mixture models publication-title: arXiv 1609 07843 – ident: ref9 doi: 10.1109/ICASSP.2018.8462506 – start-page: 4055 year: 2018 ident: ref8 article-title: Image transformer publication-title: Proc 35th Int Conf Mach Learn (ICML) – ident: ref12 doi: 10.1109/OJSSCS.2021.3119554 – year: 2017 ident: ref23 article-title: Mixed precision training publication-title: arXiv 1710 03740 – volume: 1 start-page: 9 year: 2019 ident: ref5 article-title: Language models are unsupervised multitask learners publication-title: OpenAIRE blog
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SubjectTerms	Algorithm-hardware codesign Algorithms Computational modeling Computer architecture Computer memory Data models Energy efficiency general matrix multiplication (GEMM) Hardware Memory management nonlinear function Optimization Platforms Task analysis Technology assessment Training training accelerator Transformer Transformers
Title	An Efficient Training Accelerator for Transformers With Hardware-Algorithm Co-Optimization
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